Power Analysis And Optimization - Intel Cyclone V Design Manuallines

4. Board Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
•
VCCRSTCLK_HPS
•
VCCPLL_HPS
•
VCC_AUX_SHARED
Refer to "Power-Up Sequence" in the "Power Management" chapter of Volume 1:
Device Interfaces and Integration in the Cyclone V or Arria V Device Handbook.
GUIDELINE: Consider ramp times for maximum transient currents on supplies
when designing the Power Distribution Network (PDN).
When using the PDN Tool to calculate the required target impedance of your
application's PDN for the core fabric's
maximum transient current on
Up Period parameters. This procedure relaxes the target impedance requirements
relative to the default step function analysis, resulting in a more efficient PDN with
fewer decoupling capacitors.
Initial transient current estimates can be obtained from the EPE Spreadsheet, and
more accurate analysis is possible with the PowerPlay Power Analysis Tool in Quartus
Prime when your design is closer to completion.
Refer to
Design.
Related Information
• Arria V and Cyclone V Design Guidelines
• Cyclone V Device Handbook
• Arria V Device Handbook

4.3.4. Power Analysis and Optimization

Follow the guidelines in the Power Analysis and Optimization section of the
Cyclone V Design
portion of the device.
Processor and memory clock speeds
The biggest contribution to power consumption from the HPS is the processor clock
speed and the type, size and speed of the external SDRAM program memory. Careful
selection of these system parameters to satisfy the functional and performance
requirements of the application helps to minimize system power consumption.
CPU Standby Modes and Dynamic Clock Gating
CPU standby modes and dynamic clock gating logic can be utilized throughout the MPU
subsystem. Each CPU can be placed in standby mode, Wait for Interrupt, or Wait for
Event mode to further minimize power consumption.
For more information on standby modes, refer to the
Manual (revision
Examples
VCC
AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network
Guidelines. In addition, consider the following options for the HPS
r2p0). Power Optimization Examples are available on the
web page.
supply, model the ramp time of the
VCC
using the Core Clock Frequency and Current Ramp
Cortex-A9 Technical Reference
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
Arria V and
Design
35