Hps I/O Settings: Constraints And Drive Strengths - Intel Cyclone V Design Manuallines

GUIDELINE: Ensure that you route USB, EMAC and Flash interfaces to HPS
Dedicated I/O first, starting with USB.
It is recommended that you start by routing high speed interfaces such as USB,
Ethernet, and flash to the HPS Dedicated I/O first. USB must be routed to HPS
Dedicated I/O because it is not available to the FPGA fabric. The flash boot source
must also be routed to the HPS dedicated I/O (and not any FPGA I/O) since these are
the only I/Os that are functional before the FPGA I/Os have been configured.
Note: For Cyclone V SoC U19 package (484 pin count) only one USB controller (instead of
two) is usable due to reduced number of available HPS I/O. For more information,
refer to Why can't I map USB0 to HPS IO in my Cyclone V SoC U19 package (484 pin
count)? in the Knowledge Base.
GUIDELINE: Enable the HPS GPI pins in the Platform Designer (Standard)
HPS Component if needed
By default, the HPS GPI interface is not enabled in Platform Designer (Standard). To
enable this interface, you must select the checkbox "Enable HLGPI interface" in the
Platform Designer (Standard) HPS Component for Cyclone V/Arria V. These pins are
then exposed as part of the Platform Designer (Standard) HPS Component Conduit
Interface and can be individually assigned at the top level of the design.

3.2.2. HPS I/O Settings: Constraints and Drive Strengths

GUIDELINE: Ensure that you have I/O settings for the HPS Dedicated I/O
(drive strength, I/O standard, weak pull-up enable, etc.)
The HPS pin location assignments are managed automatically when you generate the
Platform Designer (Standard) system containing the HPS. As for the HPS SDRAM, the
I/O standard and termination settings are done once you run the
"
hps_sdram_p0_pin_assignments.tcl
Designer (Standard) HPS Component has been generated.
Note:
You can locate the script "
directory once the Platform Designer (Standard) HPS Component has been generated:
<Quartus project directory>\<Platform Designer (Standard) file
name>\synthesis\submodule
Intel Quartus Prime.
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
18
3. Design Guidelines for HPS portion of SoC FPGAs
" script that is created once the Platform
hps_sdram_p0_pin_assignments.tcl
. Shown below is an example of selecting the script in
AN-796 | 2018.06.18
" in the following