Intel Cyclone V Design Manuallines page 51

5. Embedded Software Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
Figure 7. Cyclone V / Arria V SoC Golden Hardware Reference Design Overview
The GHRD has a minimal set of peripherals in the FPGA fabric, because the HPS
provides a substantial selection of peripherals. HPS-to-FPGA and FPGA-to-HPS
interfaces are configured to a 64-bit data width.
GUIDELINE: Intel recommends that you use the latest GHRD as a baseline for
new SoC FPGA hardware projects. You may then modify the design to suit
your application ends.
The GHRD can be obtained from:
Hard Processor
ARM Coretex-A9 MPCore
System
CPU0
I-Cache D-Cache I-Cache D-Cache
Trace Memory Controller
USB OTG
Gbps Ethernet
SD/MMC
HPS-to-FPGA
M
FPGA Fabric
System ID
On-Chip RAM
S
PIO LED
PIO Button
PIO DIP Switch
JTAG UART
M
Non-Secure
JTAG Master
(FPGA Only)
CPU1
L2
ROM
RAM 64 KB
FPGA Manager
DMA
Lightweight
HSP-to-FPGA
M
S
S
S
S
S
S
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
DDR
QSPI
GPIO
I2C
UART
CAN
Timers
FPGA-to-HPS
S
M
Secure
JTAG Master
(HPS Only)
Interrupt Capturer
51