Overview Of Hps Design Guidelines For Soc Fpga Design - Intel Cyclone V Design Manuallines

1. Overview of the Design Guidelines for Cyclone
AN-796 | 2018.06.18

1.2. Overview of HPS Design Guidelines for SoC FPGA design

Table 2. HPS Design Guidelines Overview
Stages of the HPS Design Flow
Hardware and Software Partitioning
HPS Pin Multiplexing and I/O
Configuration Settings
HPS Clocks and Reset Considerations
HPS EMIF Considerations
FPGA Accelerator Design
Considerations
Recommended Tools for IP
Development
®
V SoC FPGAs and Arria
Guidelines
Determine your system topology and
use it as a starting point for your HPS
to FPGA interface design.
Plan configuration settings for the HPS
system including I/O multiplexing
options, interface to FPGA and SDRAM,
clocks, peripheral settings
HPS clocks and cold and warm reset
considerations
Usage of the HPS EMIF controller and
related considerations
Design considerations to manage
coherency between FPGA accelerators
and the HPS
Signal Tap II, BFMs, System Console
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
®
V SoC FPGAs
Links
Guidelines for Interconnecting the HPS
and FPGA on page 10
Design Considerations for Connecting
Device I/O to HPS Peripherals and
Memory on page 16
HPS Clocking and Reset Design
Considerations on page 19
HPS EMIF Design Considerations
page 21
DMA Considerations on page 24
IP Debug Tools on page 26
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