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Intel Cyclone V Design Manuallines

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AN 796: Cyclone V and Arria V SoC
Device Design Guidelines
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Prime Design Suite: 18.0
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AN-796 | 2018.06.18
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Summary of Contents for Intel Cyclone V

  • Page 1 AN 796: Cyclone V and Arria V SoC Device Design Guidelines ® ® Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe AN-796 | 2018.06.18 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    1.3. Overview of Board Design Guidelines for SoC FPGA Design..........8 1.4. Overview of Embedded Software Design Guidelines for SoC FPGA Design...... 9 2. Background: Comparison between Cyclone V SoC FPGA and Arria V SoC FPGA HPS Subsystems......................10 2.1. Guidelines for Interconnecting the HPS and FPGA............. 10 2.1.1.
  • Page 3 5.4.2. Access HPS SDRAM via the FPGA-to-SDRAM Interface........67 A. Support and Documentation..................69 A.1. Support......................69 A.2. Software Documentation..................70 B. Additional Information....................71 B.1. Cyclone V and Arria V SoC Device Guidelines Revision History........71 AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 4: Overview Of The Design Guidelines For Cyclone

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 5: The Soc Fpga Designer's Checklist

    Power Analysis and Optimization on page 35 Boundary Scan for HPS Boundary Scan for HPS on page 36 Design Guidelines for HPS Interfaces HPS EMAC PHY Interfaces on page 36 continued... AN 796: Cyclone V and Arria V SoC Device Design Guidelines...
  • Page 6 Flash Device Driver Considerations Flash Device Driver Design Considerations on page 61 HPS ECC Design Considerations HPS ECC Design Considerations on page 61 HPS SDRAM Considerations HPS SDRAM Considerations on page 63 AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 7: Overview Of Hps Design Guidelines For Soc Fpga Design

    DMA Considerations on page 24 Considerations coherency between FPGA accelerators and the HPS Recommended Tools for IP Signal Tap II, BFMs, System Console IP Debug Tools on page 26 Development AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 8: Overview Of Board Design Guidelines For Soc Fpga Design

    HPS and FPGA power supplies, power analysis and power optimization Board design guidelines for HPS Includes EMAC, USB, QSPI, SD/MMC, Design Guidelines for HPS Interfaces interfaces NAND, UART and I on page 36 AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 9: Overview Of Embedded Software Design Guidelines For Soc Fpga Design

    HPS ECC Design Considerations cache data memory, flash memory page 61 HPS SDRAM Considerations Using Preloader to debug HPS SDRAM, HPS SDRAM Considerations on page Accessing the HPS SDRAM AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 10: Background: Comparison Between Cyclone V Soc Fpga And Arria V Soc Fpga Hps Subsystems

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 11 2. Background: Comparison between Cyclone V SoC FPGA and Arria V SoC FPGA HPS Subsystems AN-796 | 2018.06.18 Figure 1. HPS-FPGA Bridges All Other All Other L3 Slaves L3 Masters LWH2F Bridge L3 Slave L3 Master FPGA Fabric 32 bit...

  • Page 12: Fpga-To-Hps Sdram Access

    2. Background: Comparison between Cyclone V SoC FPGA and Arria V SoC FPGA HPS Subsystems AN-796 | 2018.06.18 2.1.1.2. HPS-to-FPGA Bridge GUIDELINE: Use the HPS-to-FPGA bridge to connect memory hosted by the FPGA to the HPS. The HPS-to-FPGA bridge allows masters in the HPS such as the microprocessor unit (MPU), DMA, or peripherals with integrated masters to access memory hosted by the FPGA portion of the SoC device.
  • Page 13 2. Background: Comparison between Cyclone V SoC FPGA and Arria V SoC FPGA HPS Subsystems AN-796 | 2018.06.18 These interfaces connect only to the HPS SDRAM subsystem so it is recommended to use them in your design if the FPGA needs high-throughput, low-latency access to the HPS SDRAM.

  • Page 14: Connecting Soft Logic To Hps Component

    2. Background: Comparison between Cyclone V SoC FPGA and Arria V SoC FPGA HPS Subsystems AN-796 | 2018.06.18 2.1.3. Connecting Soft Logic to HPS Component Designers can connect soft logic components to the HPS using the Cyclone V/Arria V HPS component in Platform Designer (Standard).

  • Page 15: Design Guidelines For Hps Portion Of Soc Fpgas

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 16: Design Considerations For Connecting Device I/O To Hps Peripherals And Memory

    3.2. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory One of the most important considerations when configuring the HPS is to understand how the I/O is organized in the Cyclone V/Arria V SoC devices. The HPS I/O is physically divided into: •...

  • Page 17: Hps Pin Assignment Design Considerations

    Datasheet. Related Information • I/O Features in Cyclone V Devices Chapter in the Cyclone V Device Handbook, Volume 1: Device Interfaces and Integration • I/O Features in Arria V Devices Chapter in the Arria V Device Handbook, Volume 1: Device Interfaces and Integration 3.2.1.

  • Page 18: Hps I/O Settings: Constraints And Drive Strengths

    For Cyclone V SoC U19 package (484 pin count) only one USB controller (instead of two) is usable due to reduced number of available HPS I/O. For more information, refer to Why can't I map USB0 to HPS IO in my Cyclone V SoC U19 package (484 pin count)? in the Knowledge Base.

  • Page 19: Hps Clocking And Reset Design Considerations

    HPS Dedicated I/O. Constraints such as drive strength, I/O standards, and weak pull-up enables are added to the Intel Quartus Prime project just like FPGA constraints and are applied to the HPS at boot time when the second stage bootloader configures the I/O.

  • Page 20: Hps Clock Planning

    HPS subsystem. HPS warm HPS_nRST and cold reset can also be asserted from internal sources such as software-initiated AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 21: Internal Clocks

    3.4. HPS EMIF Design Considerations A critical component of the HPS subsystem is the external SDRAM memory. For Cyclone V and Arria V SoC device, the HPS has a dedicated SDRAM Subsystem that interfaces with the HPS External Memory Interface I/O.
  • Page 22 Intel FPGA and SoC devices. First, filter the “Family” to select only Cyclone V /Arria V SoC device. Then, follow on by using the filter on “Interface Type” to choose only “HPS Hard Controller”...

  • Page 23: Hps Sdram I/O Locations

    AN-796 | 2018.06.18 3.4.2. HPS SDRAM I/O Locations The Cyclone V and Arria V SoC HPS External Memory Interface I/O locations are fixed, depending on the type of memory used. You can refer to the device Pin Out files, under the “...

  • Page 24: Dma Considerations

    Conduits carry signals that do not fit into any standard interface supported by Platform Designer (Standard). Examples of these are HPS peripheral external interfaces routed into the FPGA fabric or the HPS DMA peripheral request interfaces. AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 25: Managing Coherency For Fpga Accelerators

    AXI master via the ACP port increases the accelerator performance increases but only up to a point. After that point, it is no longer possible to cache the entire data packet, and the accelerator suffers performance degradation. AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 26: Fpga Access To Acp Via Axi Or Avalon-Mm

    FPGA as well. 3.7. IP Debug Tools The Intel Quartus Prime Design Software includes many IP and system-level debug tools used in FPGA hardware designs. The following tools are commonly used for system and IP debug in embedded systems: •...
  • Page 27 HPS tools that communicate over JTAG. There are two JTAG interfaces on the Cyclone V/Arria V SoC device. The first interface is connected to the FPGA side of the device, while the second interface is connected to the HPS debug access port (DAP).

  • Page 28: Board Design Guidelines For Soc Fpgas

    4.2.1. Boot Design Considerations 4.2.1.1. Boot Source GUIDELINE: Determine which boot source is to be supported. The HPS side of the Cyclone V SoC / Arria V SoC can be booted from a variety of sources, as selected by the BSEL pins: •...
  • Page 29 ROM. • Is the device verified to work and supported by software like Preloader, U-Boot and Linux ?: For supported devices, Intel provides the Preloader, U-Boot and Linux software. For other devices, this software must be developed by the user.
  • Page 30 The HPS Flash Programmer is a tool provided with SoC EDS that can be used to program QSPI and NAND flash devices on Cyclone V / Arria V SoC boards. The tool is intended to write relatively small amounts of data (for example the preloader) since it works over JTAG and has a limited speed.
  • Page 31 Boot ROM can access it on the next reset cycle without resetting or power-cycling the flash device. For detailed information about booting from QSPI, refer to CV SoC and AV Soc QSPI Boot on RocketBoards.org. AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 32: Configuration

    4. Board Design Guidelines for SoC FPGAs AN-796 | 2018.06.18 4.2.2. Configuration The Cyclone V / Arria V SoC devices support two main type sof configuration flows: • Traditional FPGA configuration • HPS-initiated FPGA configuration HPS-initiated configuration uses fast passive parallel (FPP) mode allowing the HPS to configure the FPGA using storage locations accessible to the HPS such as QSPI, SD/MMC and NAND flash.

  • Page 33: Early System And Board Planning

    GUIDELINE: For Cyclone V SoC with L power option, apply the appropriate multiplication factor when calculating the total static power. There is no L-power option in the EPE for Cyclone V, hence you need to calculate the total static power using the following steps: 1.

  • Page 34: Design Considerations For Hps And Fpga Power Supplies For Soc Fpga

    4.3.2.2. Consider Desired HPS Boot Clock Frequency Cyclone V / Arria V SoC devices support a HPS boot clock from 10-50 MHz in PLL bypass mode, and up to 400MHz in PLL Locked mode. During power up or cold reset,...

  • Page 35: Power Analysis And Optimization

    VCC_AUX_SHARED Refer to "Power-Up Sequence" in the "Power Management" chapter of Volume 1: Device Interfaces and Integration in the Cyclone V or Arria V Device Handbook. GUIDELINE: Consider ramp times for maximum transient currents on supplies when designing the Power Distribution Network (PDN).

  • Page 36: Boundary Scan For Hps

    Managing Power by Shutting Down Supplies Cyclone V SoC and Arria V SoC support the ability to power down the FPGA portion of the device, while keeping the HPS running. Refer to the Cyclone V SoC Smart...
  • Page 37 SGMII adapter is also available to automatically adapt to transceiver-based SGMII optical modules. Note: Due to an erratum in the Cyclone V/Arria V SoC device, the RMII PHY interface is not supported when routing through the HPS Dedicated I/O. RMII interface however is supported when routing through the FPGA fabric.
  • Page 38 TXD[3:0] Cyclone V/Arria V HPS Dedicated I/O does not feature programmable delay. from the Cyclone V/Arria V SoC, you must introduce the 1.0 ns PHY TX_CLK minimum input setup time in the RGMII spec. It is strongly recommended to increase this to delay to 1.5 ns to 2.0 ns.
  • Page 39 Cyclone V RGMII Example Design 4.5.1.2.1. GMII/MII MII and GMII are only available in Cyclone V/Arria V SoC by driving the EMAC signals into the FPGA core routing logic and then ultimately to FPGA I/O pins or to internal registers in the FPGA core.
  • Page 40 Designer (Standard). Instead, add the Intel HPS GMII to RGMII Converter to the Platform Designer (Standard) subsystem and connect to the HPS component’s GMII signals. The GMII to RGMII Converter uses the Intel HPS EMAC Interface Splitter in Platform Designer (Standard) to split out the...
  • Page 41 FPGA transceiver I/O pins using logic in the FPGA and the multi-gigabit transceiver I/O. While it is possible to design custom logic for this adaptation, this section describes using Platform Designer (Standard) adapter IP. AN 796: Cyclone V and Arria V SoC Device Design Guidelines...
  • Page 42 GUIDELINE: Use appropriate board-level termination on PHY outputs. Not many PHYs offer I/O tuning for their outputs to the Cyclone V/Arria V SoC, so it is wise to double check this signal path with a simulator. Place a series resistor on each signal near the PHY output pins to reduce the reflections if necessary.

  • Page 43: Usb Interface Design Guidelines

    The interface between the ULPI MAC and PHY on the Cyclone V/Arria V SoC consists of from the MAC to the PHY and STP from the MAC to the PHY.

  • Page 44: Qspi Flash Interface Design Guidelines

    Cyclone V SoC or Arria V SoC development kits. 4.5.3. QSPI Flash Interface Design Guidelines Up to four QSPI chip selects can be used with Cyclone V/Arria V SoC. The device can boot only from QSPI connected to the chip select zero.

  • Page 45: Sd/Mmc And Emmc Card Interface Design Guidelines

    Related Information • Voltage Switching (Cyclone V) Level shifting guidelines for 1.8 V SD operation in the Cyclone V HPS • Voltage Switching (Arria V) Level shifting guidelines for 1.8 V SD operation in the Arria V HPS •...

  • Page 46: Nand Flash Interface Design Guidelines

    Table 9. UART Connections to Disable Flow Control Signal Direction Connection Input Input High Input High Input High Output No-connect Output No-connect Output No-connect OUT1_N Output No-connect OUT2_N AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 47: I 2 C Interface Design Guidelines

    4.5.8. SPI Interface Design Guidelines GUIDELINE: Consider routing SPI slave signals to FPGA fabric Due to an erratum in the Cyclone V/Arria V SoC device, the SPI output enable is not connected to the SPI HPS pins. As a result, the HPS...
  • Page 48 For details about the bits in the Cyclone V ctrlr0.scph ctrlr0.scpol HPS, refer to "ctrlr0" in the "SPI Master" chapter of the Cyclone V Hard Processor System Technical Reference Manual. • ctrlr0 For details about the bits in the Arria V ctrlr0.scph...

  • Page 49: Embedded Software Design Guidelines For Soc Fpgas

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 50 The Golden Hardware Reference Design is an Intel Quartus Prime project that contains a full HPS design for the Cyclone V SoC / Arria V SoC Development Kit. The GHRD has connections to a boot source, SDRAM memory and other peripherals on the development board.
  • Page 51 HPS-to-FPGA and FPGA-to-HPS interfaces are configured to a 64-bit data width. GUIDELINE: Intel recommends that you use the latest GHRD as a baseline for new SoC FPGA hardware projects. You may then modify the design to suit your application ends.

  • Page 52: Selecting An Operating System For Your Application

    5.1.2. Selecting an Operating System for Your Application 5.1.2.1. Linux or RTOS There are a number of operating systems that support the Cyclone V SoC and Arria V SoC, including Linux and several real-time operating systems (RTOSs). For more information on Intel’s SoC Partner OS ecosystem, visit the...

  • Page 53: Assembling Your Software Development Platform For Linux

    5.1.2.3. Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP) Modes The Dual Core ARM Cortex-A9 MPCore* in the Cyclone V / Arria V HPS can support both Symmetrical Multi-processing (SMP) and Asymmetrical Multi-processing (AMP) configuration modes. In SMP mode, a single OS instance controls both cores. The SMP configuration is supported by a wide variety of operating system manufacturers and is the most common and straightforward configuration mode for multiprocessing.
  • Page 54 GSRD as a baseline project, then modify it to suit your application needs. The GSRDs target the Intel SoC Development Boards and are provided both in source and pre-compiled form. They can be obtained from GSRD User Manuals.
  • Page 55 5.1.3.3. GSRD for Linux Build Flow The figure below presents a detailed build flow for the GSRD. Refer to the GSRD User Manuals link given below for more details. AN 796: Cyclone V and Arria V SoC Device Design Guidelines...
  • Page 56 OS binary may be able to support many variations of hardware. This flexibility is particularly important when the hardware includes an FPGA. The recommended procedure for managing the Linux Device Tree is: AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 57: Assembling A Software Development Platform For A Bare-Metal Application

    1. Start with the SoC FPGA reference Device Trees provided in the Linux kernel source code that targets the Intel SoC development kits. They cover the HPS portion of the device but do not cover the FPGA portion which changes on a per- project basis.

  • Page 58: Assembling Your Software Development Platform For A Partner Os Or Rtos

    OS or RTOS. 5.1.6. Choosing Boot Loader Software The Cyclone V / Arria V SoC boot flow includes the following stages: AN 796: Cyclone V and Arria V SoC Device Design Guidelines...
  • Page 59 Figure 13. Cyclone V / Arria V SoC Boot Flow The BootROM and Preloader stages are needed for all Cyclone V SoC / Arria V SoC applications. U-boot and Linux are used by the GSRD, but a custom application may implement a different flow, such as using the Preloader to load a bare-metal application directly.

  • Page 60: Selecting Software Tools For Development, Debug And Trace

    GUIDELINE: Decide which software development tools to use, and select the tool versions. Software development tools include compilers, assemblers, linkers, and archivers. The Arm Development Studio 5* (DS-5*) Intel SoC FPGA Edition includes the following software build tools: • ARMCC Bare-metal Compiler •...

  • Page 61: Flash Device Driver Design Considerations

    The generated boot code configures, initializes and enables ECC according to user options selected during BSP generation. Custom firmware and bare metal application code access to the ECC features is facilitated with the Intel-provided HWLibs library, which provides a simple API for programming HPS software features.

  • Page 62: General Ecc Design Considerations

    GUIDELINE: The L1 and L2 cache must be configured as write-back and write-allocate for any cacheable memory region with ECC enabled. For BSPs supported by the Intel SoC FPGA EDS, you can configure your BSP for ECC support with the bsp-editor utility.

  • Page 63: Ecc For Flash Memory

    SoC FPGA Embedded Development Suite User Guide 5.4.1.1. Enable Runtime Calibration Report To enable the runtime calibration report, use your preferred editor to open the <project_folder>\software\spl_bsp\uboot-socfpga\board\altera file and configure the \socfpga\sdram\sequencer_defines.h value to RUNTIME_CAL_REPORT AN 796: Cyclone V and Arria V SoC Device Design Guidelines...
  • Page 64 Intel Quartus Prime version 14.0 and later. — PRBS31 Data pattern — Write to random address => Read from random address — Can select different coverage by changing parameter in spl.c AN 796: Cyclone V and Arria V SoC Device Design Guidelines...
  • Page 65 5. Embedded Software Design Guidelines for SoC FPGAs AN-796 | 2018.06.18 5.4.1.4. Change Data Pattern in Example Driver 1. Path for sdram_test.c <project_folder>\software\spl_bsp\uboot- socfpga\arch\arm\cpu\armv7\socfpga\sdram_test.c 2. Change the function test_rand_address AN 796: Cyclone V and Arria V SoC Device Design Guidelines...
  • Page 66 AN-796 | 2018.06.18 5.4.1.5. Example Code to Write and Read from All Addresses 5.4.1.6. Read/Write to HPS Register in Preloader Use the following function: to write to HPS register writel AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 67: Access Hps Sdram Via The Fpga-To-Sdram Interface

    Preloaders (SPL) and U-Boot generated from SoC EDS 13.1 and later contain extra functionality and built in functions to safely enable the HPS bridges. To enable the HPS FPGA-to-SDRAM bridge from the Preloader or U-Boot, follow the appropriate steps. AN 796: Cyclone V and Arria V SoC Device Design Guidelines...
  • Page 68 For more information, refer to the KDB solution: How can I enable the FPGA2SDRAM bridge on Cyclone V SoC and Arria V SoC Devices? AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 69: Support And Documentation

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 70: Software Documentation

    RocketBoards.org Boards • RocketBoards.org Projects • Intel SoC FPGA Embedded Development Suite User Guide • Download SoC EDS Getting Started tab of the Intel SoC FPGA Embedded Development Suite page AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

  • Page 71: Additional Information

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 72 "Embedded Software Design Guidelines for SoC FPGAs" chapter: — Reference DTB for NAND-based boot no longer supplied — Clarify NAND flash interface type required for booting support 2017.02.20 Initial Release AN 796: Cyclone V and Arria V SoC Device Design Guidelines...

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