Hps Pin Assignment Design Considerations - Intel Cyclone V Design Manuallines

3. Design Guidelines for HPS portion of SoC FPGAs
AN-796 | 2018.06.18
The table below summarizes the characteristics of each I/O type.
Table 7. I/O Types
Number of Available I/O
Voltages Supported
Purpose
Timing Constraints
Recommended Peripherals
Note: You can access the timing information to perform off-chip analysis by reviewing the
HPS timing in the
Related Information
• I/O Features in Cyclone V Devices
Chapter in the Cyclone V Device Handbook, Volume 1: Device Interfaces and
Integration
• I/O Features in Arria V Devices
Chapter in the Arria V Device Handbook, Volume 1: Device Interfaces and
Integration

3.2.1. HPS Pin Assignment Design Considerations

Because the HPS contains more peripherals than can all be connected to the HPS
Dedicated I/O, the HPS component in Platform Designer (Standard) offers pin
multiplexing settings as well as the option to route most of the peripherals into the
FPGA fabric. Any unused pins for the HPS Dedicated I/O with loaner capability
meanwhile can be used as general purpose I/O by the FPGA.
Note that a HPS I/O Bank can only support a single supply of either 1.2V, 1.35V, 1.5V,
1.8V, 2.5V, 3.0V, or 3.3V power supply, depending on the I/O standard required by the
specified bank. 1.35V is supported for HPS Row I/O bank only.
HPS Dedicated HPS Dedicated
Function Pins I/O with
loaner
capability
11 Up to 67
(Cyclone V
SoC) and 94
(Arria V SoC)
3.3V, 3.0V, 3.3V, 3.0V,
2.5V, 1.8V, 2.5V, 1.8V,
1.5V 1.5V
Clock, Reset, Boot source,
HPS JTAG High speed
HPS
peripherals
Fixed Fixed
JTAG QSPI, NANDx8,
eMMC, SD/
MMC, UART,
USB, EMAC
Cyclone V Device Datasheet
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
HPS External HPS General
Memory Purpose Input
Interface
Up to 86 14 (except for
Cyclone V SoC
U19 package )
LVDS I/O for Same as the
DDR3, DDR2 I/O bank
and LPDDR2 voltage used
protocols for HPS EMIF
Connect to General
SDRAM Purpose Input
Fixed for legal Fixed
combinations
DDR3, DDR2 GPI
and LPDDR2
SDRAM
or Arria V Device Datasheet.
FPGA I/O
Up to 288
(Cyclone V
SoC) and Up to
592 (Arria V
SoC)
3.3V, 3.0V,
2.5V, 1.8V,
1.5V, 1.2V
General
Purpose I/O
User defined
Slow speed
peripherals
2
(I C, SPI,
EMAC-MII)
17