Intel Cyclone V Design Manuallines page 30

4.2.1.4. Boot Clock
GUIDELINE: Determine boot clock source.
The boot clock influences the boot duration. Consider your system boot speed
requirement as the primary factor in choosing the book clock. The system boot time
requirement depends on how fast the FPGA needs to be configured for an appropriate
response time, and how quickly the HPS software must be booted. The HPS software
boot speed is influenced by the following factors:
•
Value of external clock to the HPS (i.e.
• Boot flash source interface operation frequency
Boot clock configurations are selected with the CSEL pins. Available combinations are
described in the appropriate Hard Processor System Technical Reference Manual.
Note: CSEL pins are not used when booting from FPGA fabric.
Related Information
• Cyclone V Hard Processor System Technical Reference Manual
• Arria V Hard Processor System Technical Reference Manual
4.2.1.5. CSEL Options
GUIDELINE: Provide a method to configure CSEL options.
For debugging purposes, it may be beneficial to allow setting of various CSEL values
even if the end product requires just one CSEL setting. If possible, design the board in
such a way that the CSEL configuration can be varied even if a single value will
eventually be used. This configurability may be useful for debugging and could be
done by resistors, jumpers or switches.
4.2.1.6. Selecting NAND Flash Devices
GUIDELINE: Select a NAND flash that is ONFI 1.0 compliant.
When booting from NAND, ensure that the selected device is ONFI 1.0 compliant.
The NAND device used for booting must also have a ×8 interface, and only a single
pair of
ce#
Although some non-ONFI 1.0 compliant devices are compatible with the BootROM, the
HPS Flash Programmer only supports ONFI compliant devices.
4.2.1.7. Determine Flash Programming Method
GUIDELINE: Ensure that the board is configured properly to support flash
programming.
The HPS Flash Programmer is a tool provided with SoC EDS that can be used to
program QSPI and NAND flash devices on Cyclone V / Arria V SoC boards. The tool is
intended to write relatively small amounts of data (for example the preloader) since it
works over JTAG and has a limited speed.
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
30
and pins.
rb#
4. Board Design Guidelines for SoC FPGAs
clock)
OSC1
AN-796 | 2018.06.18