Managing Coherency For Fpga Accelerators; Cache Coherency; Coherency Between Fpga Logic And Hps: Accelerator Coherency Port (Acp); Data Size Impacts Acp Performance - Intel Cyclone V Design Manuallines

3. Design Guidelines for HPS portion of SoC FPGAs
AN-796 | 2018.06.18

3.6. Managing Coherency for FPGA Accelerators

Data shared between the HPS and the FPGA logic can be modified at any time, by
either the HPS or the FPGA. Many applications require data coherency, which means
that changes are propagated throughout the system, so that every master accesses
the most up-to-date data value.
When you design for data coherency, first you must determine which data transfers
need to be coherent. By default all access between the FPGA and HPS are assumed to
be non-coherent unless coherency is explicitly managed by software or using coherent
hardware features of the HPS (SCU and ACP).
To determine if peripherals in the FPGA need coherent access to HPS memory, answer
the follow questions:
• Does the MPU need to access data generated by my FPGA peripheral?
• Does the FPGA peripheral need to access data generated by the MPU?
If the answer to either question is "Yes", the data must be coherent. You can use the
ACP to keep the FPGA coherent with cacheable data in the HPS.

3.6.1. Cache Coherency

There are several mechanisms via which coherency are maintained through the
system:
The HPS maintains cache coherency at a level 1 memory subsystem level within the
MPU subsystem. The snoop control unit (SCU) built into the MPU subsystem maintains
cache coherency between the two L1 data caches using the modified-exclusive-
shared-invalid (MESI) coherency protocol.
3.6.2. Coherency between FPGA Logic and HPS: Accelerator Coherency
Port (ACP)
The accelerator coherency port (ACP) of the SCU provides a means for other masters
in the system, including logic implemented in the FPGA fabric, to perform cache
coherent accesses. Accesses to the ACP are only unidirectional in terms of cache
coherency meaning at the time of the access the data is up to date, but the SCU is not
responsible for maintaining coherency of that data over time. For example, if a master
in the FPGA reads data from the ACP and then a processor updates that same data in
memory, then the FPGA no longer contains the most up to date copy of the data.

3.6.3. Data Size Impacts ACP Performance

Performance explorations of accelerators using ACP show that as size of packets
transferred by AXI master via the ACP port increases the accelerator performance
increases but only up to a point. After that point, it is no longer possible to cache the
entire data packet, and the accelerator suffers performance degradation.
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
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