Access Hps Sdram Via The Fpga-To-Sdram Interface - Intel Cyclone V Design Manuallines

5. Embedded Software Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
•
writel(value, address);
2.
readl
•
readl(address);
For example:
5.4.1.7. Check HPS PLL Lock Status in Preloader
•
Read HPS PLL Status Register in
— Define global variable in
— Unable to printout value in
initialized yet

5.4.2. Access HPS SDRAM via the FPGA-to-SDRAM Interface

The HPS bridges can be enabled from the Preloader (SPL/MPL) or U-Boot and in some
cases from Linux.
Note: Preloaders (SPL) and U-Boot generated from SoC EDS 13.1 and later contain extra
functionality and built in functions to safely enable the HPS bridges.
To enable the HPS FPGA-to-SDRAM bridge from the Preloader or U-Boot, follow the
appropriate steps.
to read from HPS register
clock_manager.c
and print out in
clock_manager.c
and "extern variable" in
as the UART has not been
clock_manager.c
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
spl.c
spl.c
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