Intel Cyclone V Design Manuallines page 27

3. Design Guidelines for HPS portion of SoC FPGAs
AN-796 | 2018.06.18
1. IP Creation in RTL
2. Testbench and BFM verification of the IP
3. In silicon testing of the IP using system console to drive stimuli into memory-
mapped or streaming interface
4. In silicon testing of the IP using low level software run on the processor in the HPS
In the case of Signal Tap and system console, if both use the FPGA JTAG interface to
communicate data then they can be used simultaneously. For example, you may
instrument a trigger condition in Signal Tap and cause the trigger condition to occur
via the JTAG-to-Avalon bridge IP controlled by System console. These tools are also
capable of being used simultaneously with the HPS tools that communicate over JTAG.
There are two JTAG interfaces on the Cyclone V/Arria V SoC device. The first interface
is connected to the FPGA side of the device, while the second interface is connected to
the HPS debug access port (DAP).
Related Information
• "Design Debugging Using In-System Sources and Probes" chapter of the Intel
Quartus Prime Standard Edition Handbook Volume 3: Verification
Description of Signal Tap
• Avalon-MM v2 protocol
• AXI v3 protocol
• "System Debugging Tools Overview" chapter of the Intel Quartus Prime Standard
Edition Handbook Volume 3: Verification
Description of System Console
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
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