Power-On Conditions; Channel Status Group; Channel Summary Group; Questionable Status Group - Keysight Technologies N3301A Programming Manual

Power-On Conditions

Refer to the *RST command description in chapter 4 for the power-on conditions of the status registers.

Channel Status Group

The Channel Status registers record signals that indicate abnormal operation of a specific channel of the
electronic load. As shown below, the group consists of a Condition, Event, and Enable register. The
outputs of the Channel Status registers are logically-ORed into the Channel Summary Registers.
Register Command
Condition
STAT:CHAN:COND?
Event
STAT:CHAN:EVEN?
Enable
STAT:CHAN:ENAB <n>

Channel Summary Group

The Channel Summary registers summarize the abnormal operation of all channels of the electronic load.
As shown below, the group consists of an Event and Enable register. The outputs of the Channel
Summary registers are logically-ORed into the Channel SUMmary bit (2) of the Status Byte register.
Register Command
Event
STAT:CSUM:EVEN?
Enable
STAT:CSUM:ENAB <n>

Questionable Status Group

The Questionable Status registers record signals that indicate abnormal operation of the electronic load
from all of the channels. The group consists of the same type of registers as the Channel Status group.
The outputs of the Questionable Status group are logically-ORed into the QUEStionable summary bit (3)
of the Status Byte register.
Register Command
Condition
STAT:QUES:COND?
Event
STAT:QUES:EVEN?
Enable
STAT:QUES:ENAB <n>

Standard Event Status Group

This group consists of an Event register and an Enable register that are programmed by Common
commands. The Standard Event event register latches events relating to instrument communication
status (see figure 3-4). It is a read-only register that is cleared when read. The Standard Event enable
register functions similarly to the enable registers of the Operation and Questionable status groups.
A read-only register that holds real-time status of the channel
being monitored.
A read-only register that latches any condition. It is cleared
when read.
A read/write register that functions as a mask for enabling
specific bits in the Event register.
A read-only register that latches any condition from all
channels. It is cleared when read.
A read/write register that functions as a mask for enabling
specific bits in the Enable register.
A read-only register that holds real-time logically ORed status
of all channels of the mainframe.
A read-only register that latches any condition. It is cleared
when read.
A read/write register that functions as a mask for enabling
specific bits in the Enable register.
Programming Examples - 3
Description
Description
Description
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