Changes To Figure 8 - Analog Devices EVAL-AD5696RSDZ User Manual

EVAL-AD5696RSDZ User Guide
THE SDP CONNECTOR IMPLEMENTS THE E13 CONNECTOR SPECIFICATIONS STANDARD. THIS IS A STANDARD FOR USE ACROSS ADI AND CANNOT BE MODIFIED
12C BUS 1 IS COMMON ACROSS BOTH
CONNECTORS ON SDP - PULL UP RESISTORS
REQUIRED (CONNECTED TO BLACKFIN
GPIO - USE 12C_0 FIRST)
A0
RESETB
GAIN
SPI_SEL1/SPI_SS MUST BE ONLY USED
WITH EXTERNAL SPI FLASH
E1
R12
1 2
USB_SUPPLY
1.8
C21
600OHM
C22 C23
10UF
4.7UF 0.1UF
DGND
AGND AGND
DGND
VIN: USE THIS PIN TO POWER
THE SDP REQUIRES 5V 300MA
DGND
SDP CONNECTOR
SDP
60 61
RESET_IN_N BMODE1
59 62
UART_RX UART_TX
58 63
GND GND
57 64
RESET_OUT_N SLEEP_N
56 65
EEPROM_A0 WAKE_N
55 66
NC NC
54 67 BMODE1: PULL UP WITH A 10K RESISTOR TO SET SDP
NC NC
53 68 TO BOOT FROM A SPI FLASH ON THE DAUGHTER BOARD
NC NC
52 69
GND GND
51 70
NC NC
50 71
NC CLKOUT
49 72
TMR_C TMR_D
48 73
TMR_A TMR_B
47 74
GPIO6 GPIO7
46 75
GND GND
45 76
A1
GPIO4 GPIO5
44 77
LDACB
GPIO2 GPIO3
43 78
RSTSEL
GPIO0 GPIO1
42 79
SCL_1 SCL_0
41 80
SDA_1 SDA_0
40 81
GND GND
39 82
SCLK
SPI_SEL1/SPI_SS_N SPI_CLK
38 83
SDO
SPI_SEL_C_N SPI_MISO
37 84
SDIN
SPI_SEL_B_N SPI_MOSI
36 85
SYNCB
GND SPI_SEL_A
35 86
SERIAL_INT GND
34 87 DNI
SPI_D3 SPORT_TSCLK
33 88
R20
SPI_D2 SPORT_DT0
32 89
100K
SPORT_DT1 SPORT_TFS
31 90
R0603
SPORT_DR1 SPORT_RFS
30 91
TOL=1
SPORT_TDV1 SPORT_DR0
VIO
29 92
SPORT_TDV0 SPORT_RSCLK
28 93
GND GND
27 94
PAR_FS1 PAR_CLK
26 95
PAR_FS3 PAR_FS2
25 96
PAR_A1 PAR_A0
24 97
PAR_A3 PAR_A2
23 98
GND GND
22 99 WHEN USING SPI INTERFACE, BE AWARE OF ADDING A PULL UP
PAR_CS_N PAR_INT
21 100 ON THE SPI_SEL_A/B/C LINES THAT ARE ACTIVE LOW ENABLED
PAR_RD_N PAR_WR_N
SINCE SPI IS A SHARED BUS, ENSURE THAT ANY SPI DEVICE ON DAUGHTER BOARD
20 101
PAR_D1 PAR_D0
IS NOT ACTIVELY DRIVING THE MISO DATA LINE UNLESS PROPERLY ADDRESSED WITH
19 102
PAR_D3 PAR_D2
18 103 AN ACTIVE LOW CHIP SELECT. ENSURE ALSO THAT THE SPI CLK LINE IS NOT HELD
PAR_D5 PAR_D4
HIGH OR LOW BY YOUR BOARD AT POWER UP. FAILURE TO MEET THIS
17 104
GND GND
RESULT TO A NON-FUNCTIONAL SYSTEM.
16 105
PAR_D7 PAR_D6
15 106
PAR_D9 PAR_D8
107
14
PAR_D11 PAR_D10
13 108
PAR_D13 PAR_D12
12 109
PAR_D14 GND
11 110
GND PAR_D15
10 111
PAR_D17 PAR_D16
9 112
PAR_D19 PAR_D18
8 113
PAR_D21 PAR_D20
7 114
PAR_D23 PAR_D22
6 115
GND GND
R13
5 116
USB_VBUS VIO(+3.3V)
4 117
0
GND GND
3 118
GND GND
2 119
NC NC
1
120
VIN NC
VIO: USE TO SET IO VOLTAGE MAX DRAW 20MA
FX8-120S-SV(21)
: USE ONLY TO POWER THE EEPROM(3MA MAX DRAW)
DGND
Figure 8. EVAL-AD5696RSDZ
Rev. C | Page 9 of 13
DNI
R1
R2
100K
100K
R0603
1
R0603
A0
2
TOL=1
A1
3
A2
6
SCL
7
WP
R3
100K
R0603
TOL=1 DGND
DGND
MAIN 12C BUS (CONNECTED TO BLACKFIN TWI - PULL UP RESISTORS NOT REQUIRED
VIO
CONNECT P1-P4 AND P7-P10 TO SIGNAL BUSES FOR SPI
CONNECT VCC TO 3.3V DIGITAL REFERENCE OR LEAVE FLOATING
IF VCC WILL BE USED TO POWER THE MODULE, PROVIDE PROTECTION CIRCUIT BLOCK IF POSSIBLE
Schematic—SDP Connector
VIO
C24
C25
10UF
0.1UF
U1
8
VCC
DGND
24LC32A-I/ST
TSSOP8
5
SDA
VSS
EEPROM
4
BOARD ID EEPROM (24LC32) MUST BE ON I2C BUS 0
SCL_0
SDA_0
PMOD INTERFACE TYPE 2A (EXPANDED SPI)
DNI
PMOD
1 7
SCLK_A0 LDACB
P1 P7
2 8
SDO_SDA RESETB
P2 P8
3 9
SDIN_A1 RSTSEL
P3 P9
4 10
SYNCB_SCL GAIN
P4 P10
5 11
GND GND
6 12
DGND
VCC VCC
TSW-106-08-G-D
VDD VIO
UG-726
DGND