Silicon Laboratories SI5351A/B/C Product Manual page 6

Si5351A/B/C
Table 5. Output Clock Characteristics
(V = 2.5 V ±10%, or 3.3 V ±10%, T
DD
Parameter
Frequency Range
Load Capacitance
Duty Cycle
Rise/Fall Time
Output High Voltage
Output Low Voltage
Period Jitter
Period Jitter VCXO
Cycle-to-Cycle Jitter
Cycle-to-Cycle Jitter
VCXO
RMS Phase Jitter
RMS Phase Jitter VCXO J
Table 6. Crystal Requirements
Parameter
Crystal Frequency
Load Capacitance
Equivalent Series Resistance
Crystal Max Drive Level
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device's internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitors in addition to external 2 pF load capacitors.
2. Refer to "AN551: Crystal Selection Guide" for more details.
6
= –40 to 85 °C)
A
Symbol Test Condition
F
CLK
C
L
Measured at V
DC
f
CLK
t
r
20%–80%, C
Drive Strength = 8 mA
t
f
V
OH
C
L
V
OL
J
PER
Measured over 10k cycles
J
PER_VCXO
J
CC
Measured over 10k cycles
J
CC_VCXO
J
RMS
12 kHz–20 MHz
RMS_VCXO
1,2
Preliminary Rev. 0.95
Min
0.008
—
/2,
DD
45
= 50 MHz
0.5
= 5 pF,
L
0.5
V – 0.6
DD
= 5 pF
—
—
—
—
—
—
—
Symbol Min
f 25
XTAL
C 6
L
r —
ESR
d —
L
Typ Max Units
— 160 MHz
5 15 pF
50 55 %
1 1.5 ns
1 1.5 ns
— — V
— 0.6 V
35 100 ps pk-pk
60 110 ps pk-pk
30 90 ps pk
50 95 ps pk
3.5 11 ps rms
8.5 18.5 ps rms
Typ Max Unit
— 27 MHz
— 12 pF

— 150
— 100 µW