Silicon Laboratories SI5319 Reference Manual
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Silicon Laboratories SI5319 Reference Manual

Silicon Laboratories SI5319 Reference Manual

Any-frequency precision clocks
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A
- F
P
C
NY
R E Q U E N C Y
RECISION
L O C K S
Si5316, Si5319, Si5322, S i 5 3 2 3 , S i 5 3 2 4 , S i 5 3 2 5 ,
Si5326, Si5327, Si5365, Si5366, Si5367,
Si5368, Si5369, Si5374, Si5375
F
R
M
AMILY
EFERENCE
ANUAL
Rev. 0.52 4/12
Copyright © 2012 by Silicon Laboratories
Si53xx-RM

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  • Page 1 R E Q U E N C Y RECISION L O C K S Si5316, Si5319, Si5322, S i 5 3 2 3 , S i 5 3 2 4 , S i 5 3 2 5 , Si5326, Si5327, Si5365, Si5366, Si5367, Si5368, Si5369, Si5374, Si5375...
  • Page 2 Si53xx-RM Rev. 0.52...

  • Page 3: Table Of Contents

    6.1.1. Clock Multiplication (Si5316) ........... 49 6.1.2. Clock Multiplication (Si5322, Si5323, Si5365, Si5366) ....... 51 6.1.3.
  • Page 4 7.1.4. Loop Bandwidth (Si5319, Si5326, Si5368, Si5375) ........
  • Page 5 7.6.4. VCO Freeze (Si5319, Si5325, Si5367, Si5375)........
  • Page 6 Appendix A—Narrowband References ........118 Appendix B—Frequency Plans and Jitter Performance (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, Si5375) .
  • Page 7 Figure 11. Si5367 Clock Multiplier Block Diagram ....... . .
  • Page 8 Figure 52. Sinewave External Clock Circuit ........
  • Page 9 Figure 97. Output Clock Routing ........
  • Page 10 Table 19. Clock Output Divider Control (DIV34) ........
  • Page 11 Table 71. Si5319, Si5324, Pullup/Down ........

  • Page 12: Any-Frequency Precision Clock Product Family Overview

    Minimum Clock (SMC) FOS thresholds are supported. The Si5319, Si5323, Si5324, Si5326, Si5366, Si5368, and Si5369 provide a digital hold capability that allows the device to continue generation of a stable output clock when the selected input reference is lost. During digital hold,...
  • Page 13 LOS and FOS monitoring is available for these devices, as described above. The Si5374 and Si5375 are quad DSPLL versions of the Si5324 and Si5319, respectively. Each of the four DSPLLs can operate at completely independent frequencies. The only resources that they share are a common C bus and a common XA/XB jitter reference oscillator.

  • Page 14: Table 1. Product Selection Guide

    1PLL, 2 | 2 0.008–644 Si5316 1PLL, 2 | 1 19–710 Si5317 1PLL, 1 | 2 1–710 Si5319 C/SPI 1PLL, 1 | 1 0.002–710 0.002–1417 Si5323 1PLL, 2 | 2 0.008–707 0.008–1050 Si5324 C/SPI 1PLL, 2 | 2 0.002–710 0.002–1417...

  • Page 15: Wideband Devices

    1. Maximum input and output rates may be limited by speed rating of device. See each device’s data sheet for ordering information. 2. Requires external low-cost, fixed frequency 3rd overtone 114.285 MHz crystal or reference clock. See "Table 60.XA/XB Reference Sources and Frequencies" on page 118.

  • Page 16: Any-Frequency Clock Family Members

    The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC- 192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitter-attenuated clock output at the same frequency. Within each of these clock ranges, the device can be tuned approximately 14% higher than nominal SONET/SDH frequencies, up to a maximum of 710 MHz in the 622 MHz range.

  • Page 17: Si5319

    The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock source for frequency synthesis.

  • Page 18: Si5322

    The DSPLL loop bandwidth is digitally selectable from 150 kHz to 1.3 MHz. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5322 is ideal for providing low jitter clock multiplication in high performance timing applications. See "6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)" on page 49 for a complete description.

  • Page 19: Si5323

    8 kHz to 707 MHz and generates two frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, and broadcast video rates. The DSPLL loop bandwidth is digitally selectable, providing jitter performance optimization at the application level.

  • Page 20: Si5324

    4 Hz. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5324 is ideal for providing clock multiplication and jitter attenuation in high-performance timing applications. See "7. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)" on page 75 for a complete description.

  • Page 21: Si5325

    150 kHz to 1.3 MHz. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5325 is ideal for providing clock multiplication in high performance timing applications. See "7. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)" on page 75 for a complete description.

  • Page 22: Si5326

    60 Hz to 8 kHz, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock multiplication and jitter attenuation in high-performance timing applications. See "7. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)"...

  • Page 23: Si5327

    The Si5327 features loop bandwidth values as low as 4 Hz. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5327 is ideal for providing clock multiplication and jitter attenuation in high-performance timing applications. See "7. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)"...

  • Page 24: Si5365

    The Si5365 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5365 accepts four clock inputs ranging from 19.44 MHz to 707 MHz and generates five frequency-multiplied clock outputs ranging from 19.44 MHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, and broadcast video rates.

  • Page 25: Si5366

    SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5366 accepts four clock inputs ranging from 8 kHz to 707 MHz and generates five frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, and broadcast video (HD SDI, 3G SDI) rates.

  • Page 26: Si5367

    150 kHz to 1.3 MHz. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5367 is ideal for providing clock multiplication in high performance timing applications. See "7. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)" on page 75 for a complete description.

  • Page 27: Si5368

    Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5368 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. See "7. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)" on page 75 for a complete description.

  • Page 28: Si5369

    In general, the Si5374 can be viewed as a quad version of the Si5324 and the Si5375 can be viewed as a quad version of the Si5319. However, there are not exactly the same. This is an overview of the differences: 1.

  • Page 29: Si5374

    The Si5374 is a highly integrated, 4-PLL jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts two input clocks ranging from 2 kHz to 710 MHz and generates two independent, synchronous output clocks ranging from 2 kHz to 808 MHz. Each DSPLL provides virtually any frequency translation across this operating range.

  • Page 30: Si5375

    The Si5375 is a highly integrated, 4-PLL jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts an input clock ranging from 2 kHz to 710 MHz and generates an output clock ranging from 2 kHz to 808 MHz. Each DSPLL provides virtually any frequency translation combination across this operating range.

  • Page 31: Table 3. Recommended Operating Conditions 1

    4. Device Specifications The following tables are intended to simplify device selection. The specifications in the individual device data sheets take precedence over this document. Refer to the respective device data sheet for devices not listed in the tables below. Table 3.

  • Page 32: Table 4. Dc Characteristics

    Si53xx-RM Table 4. DC Characteristics Parameter Symbol Test Condition Supply Current LVPECL Format (Independent of 622.08 MHz Out Supply Voltage) LVPECL Format 622.08 MHz Out Only 1 CKOUT CMOS Format 19.44 MHz Out CMOS Format 19.44 MHz Out Only 1 CKOUT CKIN_n Input Pins Input Common Mode Voltage...
  • Page 33 Table 4. DC Characteristics (Continued) Parameter Symbol Test Condition Output Clocks (CKOUTn—See “8.2. Output Clock Drivers” for Configuring Output Drivers for LVPECL/CML/LVDS/CMOS) LVPECL 100  Common Mode load line-to-line LVPECL 100  Differential Output Swing load line-to-line LVPECL 100 ...
  • Page 34 Si53xx-RM Table 4. DC Characteristics (Continued) Parameter Symbol Test Condition Output Drive Current (CMOS driv- Driving into CKO- ing into CKO output low or CKO- or CKO for output high. put high. CKOUT+ CKOUT+ and CKOUT- shorted shorted externally. externally) ICMOS[1:0] = 11 ICMOS[1:0] = 10 ICMOS[1:0] = 01...
  • Page 35 Table 4. DC Characteristics (Continued) Parameter Symbol Test Condition Input Mid Current Input High Current LVCMOS Output Pins Output Voltage Low Output Voltage High Tri-State Leakage Current Notes: 1. Refer to Section 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V. 2.

  • Page 36: Table 5. Dc Characteristics—Microprocessor Devices (Si5324, Si5325, Si5367, Si5368)

    Si53xx-RM Table 5. DC Characteristics—Microprocessor Devices (Si5324, Si5325, Si5367, Si5368) Parameter Symbol C Bus Lines (SDA, SCL)* Input Voltage Low ILI2C Input Voltage High IHI2C Hysteresis of Schmitt trig- HYSI2C ger inputs Output Voltage Low OHI2C *Note: When selecting pull-up resistors for the two I This does not apply to the SDA pin.

  • Page 37: Figure 18. Spi Timing Diagram

    SCLK Table 7. DC Characteristics—Narrowband Devices (Si5316, Si5319, Si5323, Si5366, Si5368) Parameter Symbol Single-Ended Reference Clock Input Pin XA (XB with cap to gnd) Input Resistance Input Voltage Level Limits Input Voltage Swing Differential Reference Clock Input Pins (XA/XB) Differential Input Voltage...

  • Page 38: Figure 19. Frame Synchronization Timing

    Si53xx-RM CLKOUT_2 FSYNC CLKIN_4* FSSU FSYNC_ALIGN LATF FSYNCOUT* Fixed number of CLKOUT_2 clock cycles. * CLKIN_2 and CLKIN_4 are the active input clock and frame sync pair in this example Figure 19. Frame Synchronization Timing Rev. 0.52...

  • Page 39: Table 8. Ac Characteristics—All Devices

    Table 8. AC Characteristics—All Devices Symbol Test Condition Parameter Input Frequency When used as frame synchronization input CKIN_n Input Pins Input Duty Cycle Whichever is smaller (Minimum Pulse (i.e., the 40% / 60 % Width) limitation applies only to high frequency clocks) , N3 >...
  • Page 40 Si53xx-RM Table 8. AC Characteristics—All Devices (Continued) Symbol Test Condition Parameter LVCMOS Pins Input Capacitance Minimum Reset RSTMN Pulse Width Reset to Micropro- READY cessor Access Ready LVCMOS Output Pins LOSn Trigger From last CKIN_n Window to internal detection From last CKIN_n  to internal detection TRIG From last CKIN_n ...
  • Page 41 CKIN to LOL; BW = 100 Hz Pin Reset or READY Register Reset to Microprocessor Access Ready Reset to first  on Valid, stable clock on START CKOUT Minimum Reset RSTMIN Pulse Width Start of ICAL to of Lock Time...
  • Page 42 Si53xx-RM Table 8. AC Characteristics—All Devices (Continued) Symbol Test Condition Parameter Output Phase Max phase changes Change due to from –40 to +85 °C TEMP Temperature Vari- ation Jitter Tolerance Phase Noise 1 kHz Offset fout = 622.08 MHz 10 kHz Offset 100 kHz Offset 1 MHz Offset Subharmonic...

  • Page 43: Table 10. Jitter Generation (Si5322, Si5325, Si5365, Si5367)

    Jitter Gen OC-48 Notes: 1. Test condition: f = 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20–80%), LVPECL clock output. 2. BWSEL [1:0] loop bandwidth settings provided in Pin Descriptions. 3. 114.285 MHz 3rd OT crystal used as XA/XB input.

  • Page 44: Table 11. Thermal Characteristics

    Table 11. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol Test Condition Devices  Still Air Si5316, Si5319, Si5322, Si5323, Si5324, Si5325 Si5365, Si5366, Si5367, Si5368  Still Air Si5316, Si5319, Si5322, Si5323, Si5324, Si5325 Rev.

  • Page 45: Dspll (All Devices)

    All members of the Any-Frequency Precision Clocks family incorporate a phase-locked loop (PLL) that utilizes Silicon Laboratories' third generation DSPLL technology to eliminate jitter, noise, and the need for external VCXO and loop filter components found in discrete PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in discrete PLL designs.

  • Page 46: Clock Multiplication

    5.1. Clock Multiplication Fundamental to these parts is a clock multiplication circuit that is simplified in Figure 21. By having a large range of dividers and multipliers, nearly any output frequency can be created from a fixed input frequency. For typical telecommunications and data communications applications, the hardware control parts (Si5316, Si5322, Si5323, Si5365, and Si5366) provide simple pin control.

  • Page 47: Pll Performance

    5.2.1. Jitter Generation Jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock. Generated jitter arises from sources within the VCO and other PLL components. Jitter generation is a function of the PLL bandwidth setting.

  • Page 48: Jitter Tolerance

    Si53xx-RM 5.2.3. Jitter Tolerance Jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock before the DSPLL loses lock. The tolerance is a function of the jitter frequency, because tolerance improves for lower input jitter frequency.

  • Page 49: Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)

    The device accepts dual input clocks in the 19, 39, 78, 155, 311, or 622 MHz frequency range and generates a de- jittered output clock at the same frequency. The frequency range is set by the FRQSEL [1:0] pins, as shown in Table 13.

  • Page 50: Figure 24. Si5316 Divisor Ratios

    The Si5316 can accept a CKIN1 input at a different frequency than the CKIN2 input. The frequency of one input clock can be 1x, 4x, or 32x the frequency of the other input clock. The output frequency is always equal to the lower of the two clock inputs and is set via the FRQSEL [1:0] pins.

  • Page 51: Clock Multiplication (Si5322, Si5323, Si5365, Si5366)

    6.1.2. Clock Multiplication (Si5322, Si5323, Si5365, Si5366) These parts provide flexible frequency plans for SONET, DATACOM, and interworking between the two (Table 16, Table 17, and Table 18 respectively). The CKINn inputs must be the same frequency as specified in the tables. The outputs are the same frequency;...
  • Page 52 Si53xx-RM Table 16. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) FRQSEL [3:0]  LLHM 19.44  LLHH  LMLL  LMLM LMLH LMML LMMM  LMMH  LMHL LMHM LMHH LHLL  LHLM  LHLH  LHML 38.88  LHMM ...
  • Page 53 Table 16. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) FRQSEL [3:0]  MLLM 77.76  MLLH  MLML  MLMM  MLMH MLHL MLHM  MLHH  MMLL  MMLM MMLH MMML  MMMM 155.52  MMMH  MMHL  MMHM ...
  • Page 54 Si53xx-RM Table 16. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) FRQSEL [3:0] HLLL 167.33  MMHM HLLM  MHML HLLH 168.04  MMHM HLML  MHML  HLMM 311.04  HLMH  HLHL HLHM HLHH  HMLL 622.08  HMLM ...
  • Page 55 Table 16. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) FRQSEL [3:0] HHLH 669.33  HMML HHML  HMMH HHMM 672.16  HMML HHMH  HMMH Mult Factor Nominal All Devices CKOUT5 (CK_CONF = 0) 1/4 x 237/255 155.52 167.33 237/255 622.08 669.33...

  • Page 56: Table 17. Datacom Clock Multiplication Settings (Frqtbl = M, Ck_Conf = 0)

    Si53xx-RM Table 17. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF = 0) Setting FRQSEL[3:0] LLLL LLLM LLLH LLML LLMM LLMH LLHL LLHM LLHH LMLL LMLM LMLH LMML LMMM LMMH LMHL LMHM LMHH LHLL LHLM LHLH LHML LHMM LHMH LHHL...
  • Page 57 Table 17. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF = 0) (Continued) Setting FRQSEL[3:0] MLHM MLHH MMLL MMLM MMLH MMML MMMM MMMH MMHL MMHM MMHH MHLL MMMM MMMH MMHL MMHM MMHH MHLL MHLM MHLH MHML MHMM MHMH MHHL MHHM...
  • Page 58 Si53xx-RM Table 17. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF = 0) (Continued) Setting FRQSEL[3:0] HLML HLMM HLMH HLHL MHMM HLHM HLLL HLLM HLLH MHMM HLHH HLMM HLMH HLHL MHMM HMLL HMLM HMLH HMML HMMM HMMH HMHL HMHM HMML...
  • Page 59 Table 17. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF = 0) (Continued) Setting FRQSEL[3:0] HHML HHMM HHMH HMML HHHL HMMM HHHM HHLL HHLM HMML HHLH HMMM HHHH HHMM HHMH HMML HHHL HMMM (MHz) Mult Factor 693.48 1/5 x 64/66 x 237/255 1/4 x 64/66 x 237/255 ...

  • Page 60: Table 18. Sonet To Datacom Clock Multiplication Settings

    Si53xx-RM Table 18. SONET to Datacom Clock Multiplication Settings Setting FRQSEL[3:0] LLLL LLLM LLLH LLML LLMM LLMH LLHL LLHM LLHH LMLL LMLM LMLH LMML LMMM LMMH LMHL LMHM LMHH LHLL LHLM LHLH LHML LHMM LHMH LHHL LHHM LHHH MLLL MLLM...
  • Page 61 Table 18. SONET to Datacom Clock Multiplication Settings (Continued) Setting FRQSEL[3:0]  MLML 62.500  MLMM MLMH 74.176 MLHL MLHM MLHH 74.250 MMLL MMLM MMLH 77.760 MMML MMMM MMMH MMHL MMHM MMHH MHLL MHLM MHLH MHML MHMM MHMH MHHL (MHz)
  • Page 62 Si53xx-RM Table 18. SONET to Datacom Clock Multiplication Settings (Continued) Setting FRQSEL[3:0] MHHM MHHH HLLL HLLM HLLH HLML HLMM HLMH HLHL HLHM HLHH HMLL HMLM HMLH HMML HMMM (MHz) Mult Factor 155.520 15625/15552 31875/31104 15625/15552 x 66/64 31875/31104 x 66/64...

  • Page 63: Ckout3 And Ckout4 (Si5365 And Si5366)

    6.1.6. Narrowband Performance (Si5316, Si5323, Si5366) The DCO uses the reference clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins support either a crystal oscillator or an input buffer (single-ended or differential) so that an external oscillator can be used as the reference source.

  • Page 64: Pll Self-Calibration

    Internal DSPLL registers out-of-range, indicating the need to relock the DSPLL. In any of the above cases, an internal self-calibration will be initiated if a valid input clock exists (no input alarm) and is selected as the active clock at that time. For the Si5316, Si5323 and Si5366, the external crystal or reference clock must also be present for the self-calibration to begin.

  • Page 65: Table 20. Si5316, Si5322, And Si5323 Pins And Reset

    Table 20. Si5316, Si5322, and Si5323 Pins and Reset Pin # Si5316 Pin Si5322 Pin Name Name FRQTBL RATE 0 DBL_BY DBL2_BY RATE1 BWSEL0 BWSEL0 BWSEL1 BWSEL1 FRQSEL0 FRQSEL0 FRQSEL1 FRQSEL1 FRQSEL2 FRQSEL3 SFOUT1 SFOUT0 Table 21. Si5365 and Si5366 Pins and Reset Pin # Si5365 Pin Name Si5366 Pin Name...

  • Page 66: Pin Control Input Clock Control

    CS_CA (Si5322, Si5323) The manual input clock selection settings for the Si5365 and the Si5366 are shown in Table 23. The Si5366 has two modes of operation (See Section “6.5. Frame Synchronization (Si5366)”). With CK_CONF = 0, any of the four input clocks may be selected manually;...

  • Page 67: Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366)

    Setting AUTOSEL to M or H, changes the CSn_CAm pins to output pins that indicate the state of the automatic clock selection (See Table 25 and Table 26). Digital hold is indicated by all CnB signals going high after a valid ICAL.

  • Page 68: Hitless Switching With Phase Build-Out (Si5323, Si5366)

    At the time a clock switch occurs, the phase detector circuitry knows both the input-to-output phase relationship for the original input clock and for the new input clock. The phase detector circuitry locks to the new input clock at the new clock's phase offset so that the phase of the output clock is not disturbed.

  • Page 69: Digital Hold/Vco Freeze

    6.4.1. Narrowband Digital Hold (Si5316, Si5323, Si5366) If an LOS or FOS condition exists on the selected input clock, the device enters digital hold. In this mode, the device provides a stable output frequency until the input clock returns and is validated. When the device enters digital hold, the internal oscillator is initially held to its last frequency value.

  • Page 70: Output Phase Adjust (Si5323, Si5366)

    The FS_ALIGN pin controls the realignment of FS_OUT to the active CKIN3 or CKIN4 input. The currently active frame sync input is determined by which input clock is currently being used by the PLL. For example, if CKIN1 is being selected as the PLL input, CKIN3 is the currently-active frame sync input. If neither CKIN3 or CKIN4 are currently active (digital hold), the realignment request is ignored.

  • Page 71: Disabling Fs_Out (Si5366)

    The FS_OUT maybe disabled via the DBLFS pin, see Table 29. The additional state (M) provided allows for FS_OUT to drive a CMOS load while the other clock outputs use a different signal format as specified by the SFOUT[1:0] pins.

  • Page 72: Pll Bypass Mode

    6.9.1.1. Narrowband LOS Algorithm (Si5316, Si5323, Si5366) The LOS circuitry divides down each input clock to produce an 8 kHz to 2 MHz signal. (For the Si5316, the output of divider N3 (See Figure 1) is used.) The LOS circuitry over samples this divided down input clock using a 40 MHz clock to search for extended periods of time without input clock transitions.

  • Page 73: Fsync Align Alarm (Si5366 And Ck_Conf = 1 And Frqtbl = L)

    FS_OUT will include a fixed number of high-speed clock cycles, even if input clock switches are performed. If many clock switches are performed, it is possible that the input sync to output sync phase relationship will shift due to the accumulated residual phase transients of the phase build-out circuitry. The internal ALIGN_INT signal is asserted when the accumulated phase errors exceeds two cycles of CKOUT2.

  • Page 74: Device Reset

    The PLL lock detection algorithm indicates the lock status on the LOL output pin. The algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. If the time between two consecutive phase cycle slips is greater than the Retrigger Time, the PLL is in lock. The LOL output has a guaranteed minimum pulse width as shown in (Table 8, “AC Characteristics—All Devices”).

  • Page 75: Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)

    The input-to-output skew for wideband parts is not controlled. Refer to Figure 25. The selected input clock passes through the N3 input divider and is provided to the DSPLL. The input-to-output clock multiplication ratio is defined as follows:...

  • Page 76: Narrowband Parts (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)

    Si5327, Si5366, Si5368, Si5369, Si5374, and Si5375)" on page 112. Refer to Figure 26 Narrowband PLL Divider Settings (Si5319, Si5324, Si5326, Si5327, Si5368, Si5374, Si5375), a simplified block diagram of the device and Table 35 and Table 36 for frequency and divider limits. The PLL dividers and their associated ranges are listed in the diagram.

  • Page 77: Figure 26. Narrowband Pll Divider Settings (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)

    Si5319, Si5326, Si5368 Note: There are multiple outputs at different frequencies because of limitations caused by the DCO and N1_HS. Figure 26. Narrowband PLL Divider Settings (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375) Table 35. Narrowband Frequency Limits Signal CKINn Note: Fmax = 808 MHz for the Si5327, Si5374 and Si5375.

  • Page 78: Loop Bandwidth (Si5319, Si5326, Si5368, Si5375)

    In any of the above cases, an internal self-calibration will be initiated if a valid input clock exists (no input alarm) and is selected as the active clock at that time. The external crystal or reference clock must also be present for the self-calibration to begin (LOSX_INT = 0 [narrowband only]).

  • Page 79: Input Clock Stability During Internal Self-Calibration

    7.2.2. Input Clock Stability during Internal Self-Calibration An ICAL must occur when the selected active CKINn clock is stable in frequency and with a frequency value that is within the operating range that is reported by DSPLLsim. The other CKINs must be stable in frequency (< 100 ppm from nominal) or squelched during an ICAL.

  • Page 80: Input Clock Configurations (Si5367 And Si5368)

    CKOUT_ALWAYS_ON Notes: 1. Case 1 should be selected when an output clock is not desired until the part has been initialized after power-up, but is desired all of the time after initialization. 2. Case 2 should be selected when an output clock is never desired during an any ICAL. Case 2 will only generate outputs when the outputs are at the correct output frequency.

  • Page 81: Manual Clock Selection (Si5324, Si5325, Si5326, Si5367, Si5368, Si5369, Si5374)

    Register Bits CK_CONFIG_REG = 0 Note: Setting the CKSEL_PIN register bit to one allows the CS [1:0] pins to continue to control input clock selection. If CS_PIN is set to zero, the CKSEL_REG[1:0] register bits perform the input clock selection function.

  • Page 82: Automatic Clock Selection (Si5324, Si5325, Si5326, Si5367, Si5368, Si5369, Si5374)

    Table 39. Manual Input Clock Selection (Si5324, Si5325, Si5326, Si5374) CKSEL_REG or CS pin If the selected clock enters an alarm condition, the PLL enters digital hold mode. The CKSEL_REG[1:0] controls are ignored if automatic clock selection is enabled. 7.4.2. Automatic Clock Selection (Si5324, Si5325, Si5326, Si5367, Si5368, Si5369, Si5374) The AUTOSEL_REG[1:0] register bits sets the input clock selection mode as shown in Table 40.

  • Page 83: Hitless Switching With Phase Build-Out (Si5324, Si5326, Si5327, Si5368, Si5369, Si5374)

    At the time a clock switch occurs, the phase detector circuitry knows both the input-to-output phase relationship for the original input clock and for the new input clock. The phase detector circuitry locks to the new input clock at the new clock's phase offset so that the phase of the output clock is not disturbed.

  • Page 84: Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374 And Si5375 Free Run Mode

    Si53xx-RM 7.5. Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374 and Si5375 Free Run Mode Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375 C K IN 1 C K IN 2 Figure 29. Free Run Mode Block Diagram  CKIN2 has an extra mux with a path to the crystal oscillator output.

  • Page 85: Free Run Reference Frequency Constraints

    For hitless switching, to meet all published specifications, the XA/XB frequency divided by N32 should match the CLKIN  frequency divided by N31. If they do not match, the clock switch will still be well-behaved.  Other than the above, the absolute accuracy of the XA/XB Frequency Max 125.5 MHz...

  • Page 86: Digital Hold

    7.6.1.1. Digital Hold Detailed Description (Si5324, Si5326, Si5327, Si5368, Si5369, Si5374) In this mode, the device provides a stable output frequency until the input clock returns and is validated. Upon entering digital hold, the internal DCO is initially held to its last frequency value, M (See Figure 30). Next, the DCO slowly transitions to a historical average frequency value supplied to the DSPLL, M , as shown in Figure 30.

  • Page 87: Table 42. Digital Hold History Delay

    HIST_DEL[4:0] History Delay Time (ms) 00000 0.0001 00001 0.0002 00010 0.0004 00011 0.0008 00100 0.0016 00101 0.0032 00110 0.0064 00111 01000 01001 01010 01011 01100 01101 01110 01111 Table 43. Digital Hold History Averaging Time HIST_AVG[4:0] History Averaging Time (ms) 00000 0.0000 00001...

  • Page 88: History Settings For Low Bandwidth Devices (Si5324, Si5327, Si5369, Si5374)

    Si5325 and Si5367, the Si5319’s VCO freeze is controlled by the XA/XB reference (which is typically a crystal) resulting in greater stability. For the Si5319, Si5327, and Si5375, VCO freeze is similar to the Digital Hold function of the Si5326, Si5368, and Si5369 except that the HIST_AVG and HIST_DEL registers do not exist.

  • Page 89: Output Phase Adjust (Si5326, Si5368)

    100 x 83 msec = 8.3 sec. If it is necessary to set the high-speed output clock divider N1_HS to divide-by-4 in order to achieve the desired overall multiplication ratio and output frequency, only phase increments are allowed and negative settings in the CLAT register or attempts to decrement the phase via writes to the CLAT register will be ignored.

  • Page 90: Independent Skew (Si5324, Si5326, Si5368, Si5369, Si5374)

    5 GHz and N1_HS = (4, 5, 6, …, 11), the resolution varies from approximately 800 ps to 2.2 ns depending on the PLL divider settings. Silicon Laboratories' PC-based configuration software (DSPLLsim) provides PLL divider settings for each frequency translation, if applicable. If more than one set of PLL divider settings is available, selecting the combination with the lowest N1_HS value provides the finest resolution for output clock phase offset control.

  • Page 91: Figure 32. Frame Sync Frequencies

    Typically the same frequency Figure 32. Frame Sync Frequencies CKINn Frequency (kHz) 2–4 4–8 8–16 16–32 32–64 64–128 128–256 256–512   NC2_LS NC2_LS   NC5_LS NC5_LS to align to align Clock select Clock select Rev. 0.52 Si53xx-RM Divisor CKOUT2 FS_OUT...

  • Page 92: Fsync Realignment (Si5368)

    Si53xx-RM The NC5_LS divider uses CKOUT2 as its clock input to derive FS_OUT. The limits for the NC5_LS divider are NC5_LS = [1, 2, 4, 6, …, 2 < 710 MHz CKOUT2 Note that when in frame synchronization realignment mode, writes to NC5_LS are controlled by FPW_VALID. See section “7.8.4.

  • Page 93: Fsync Skew Control (Si5368)

    FSYNC_SWTCH_REG = 0. The frequency offset (FOS) alarms for CKIN1 and CKIN2 can also be included in the state machine decision making as described in Section “7.11. Alarms (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)”; however, in frame sync mode (CK_CONFIG_REG = 1), the FOS alarms for CKIN3 and CKIN4 are ignored.

  • Page 94: Output Clock Drivers (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)

    Si53xx-RM 7.9. Output Clock Drivers (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375) The device includes a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML, and CMOS formats. The signal format of each output is individually configurable through the SFOUTn_REG[2:0] register bits, which modify the output common mode and differential signal swing.

  • Page 95: Pll Bypass Mode (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)

    Si5374, Si5375) The device supports a PLL bypass mode in which the selected input clock is fed directly to the output buffers, bypassing the DSPLL. In PLL bypass mode, the input and output clocks will be at the same frequency. PLL bypass mode is useful in a laboratory environment to measure system performance with and without the jitter attenuation provided by the DSPLL.

  • Page 96: Fos Algorithm (Si5324, Si5325, Si5326, Si5368, Si5369, Si5374)

    To facilitate automatic hitless switching, the LOS trigger time can be significantly reduced by using the default LOS option (LOSn_EN = 11). The LOS circuitry divides down each input clock to produce a 2 kHz to 2 MHz signal. The LOS circuitry over samples this divided down input clock using a 40 MHz clock to search for extended periods of time without input clock transitions.

  • Page 97: Figure 33. Fos Compare

    Both the FOS reference and the FOS monitored clock must be divided down to the same clock rate and this clock rate must be between 10 MHz and 27 MHz. As can be seen in Figure 33, the values for P and Q must be selected so that the FOS comparison occurs at the same frequency.

  • Page 98: C1B, C2B (Si5319, Si5324, Si5325, Si5326, Si5327, Si5374, Si5375)

    FOS1_INT and FOS2_INT register bits do not affect the C1B and C2B alarm outputs, respectively. Once an LOS or FOS alarm is asserted on one of the input clocks, it is held high until the input clock is validated over a designated time period. The validation time is programmable via the VALTIME[1:0] register bits as shown in Table 48 on page 95.

  • Page 99: C1B, C2B, C3B, Alrmout (Si5368 [Ck_Config_Reg = 1])

    ALRMOUT at the output even if ALRMOUT_PIN = 1. Once an LOS or FOS alarm is asserted for one of the input clocks, it is held high until the input clock is validated over a designated time period. The validation time is programmable via the VALTIME[1:0] register bits as shown in Table 8, “AC Characteristics—All Devices”.

  • Page 100: Device Interrupts

    Si53xx-RM Table 54. Lock Detect Retrigger Time (LOCKT) LOCKT[2:0] 7.11.9. Device Interrupts Alarms on internal real-time status bits such as LOS1_INT, FOS1_INT, etc. cause their associated interrupt flags (LOS1_FLG, FOS1_FLG, etc.) to be set and held. The interrupt flag bits can be individually masked or unmasked with respect to the output interrupt pin.

  • Page 101: I 2 C Serial Microprocessor Interface

    C control mode (CMODE = L), the control interface to the device is a 2-wire bus for bidirectional communication. The bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL). Both lines must be connected to the positive supply via an external pull-up. In addition, an output interrupt (INT) is provided with selectable active polarity (determined by INT_POL bit).

  • Page 102: Serial Microprocessor Interface (Spi)

    SDI pin MSB first. The SDO pin will remain high impedance during write operations. Data always transitions with the falling edge of the clock and is latched on the rising edge. The clock should return to a logic high when no transfer is in progress.

  • Page 103: Default Device Configuration

    To simplify frequency planning, loop bandwidth selection, and general device configuration, of the Any-Frequency Precision Clocks. Silicon Laboratories has a configuration utility - DSPLLsim for the Si5319, Si5325, Si5326, Si5327, Si5367, Si5368 and Si5369. For the Si5374 and Si5375, there is a different configuration utility - Si537xDSPLLsim.

  • Page 104: High-Speed I/O

    8. High-Speed I/O 8.1. Input Clock Buffers Any-Frequency Precision Clock devices provide differential inputs for the CKINn clock inputs. These inputs are internally biased to a common mode voltage and can be driven by either a single-ended or differential source.

  • Page 105: Figure 40. Cml/Lvds Termination (1.8, 2.5, 3.3 V)

    Recalculate resistor values for other drive strengths Additional Notes: 1. Attenuation circuit limits overshoot and undershoot. 2. Use only with ~50% duty cycle clock signals. 3. Assumes the CMOS output can drive 8 mA. Figure 41. CMOS Termination (1.8, 2.5, 3.3 V)

  • Page 106: Output Clock Drivers

    Si5366 and Si5368 when CKOUT5 is configured as FS_OUT (frame sync) because it can a have a duty cycle significantly different from 50%. Si53xx Figure 42. Typical Output Circuit (Differential) SFOUTn Pin Settings SFOUTn_REG [2:0] Settings (Si5319, Si5325, SI5326, Si5327, Si5367, Si5368, Si5369, Si5374, All Others  Z0 = 50 ...

  • Page 107: Figure 43. Differential Output Example Requiring Attenuation

    Si53xx All resistors are located next to RCVR Figure 43. Differential Output Example Requiring Attenuation Si53xx Figure 44. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together) Unused output drivers should be powered down, per Table 57, or left floating. The pin-controlled parts have a DBL2_BY pin that can be used to disable CKOUT2.

  • Page 108: Typical Clock Output Scope Shots

    Si53xx-RM Output Disable 8.2.3. Typical Clock Output Scope Shots Table 58. Output Format Measurements Name SFOUT Pin Reserved LVDS LVPECL Reserved Low Swing LVDS CMOS Disable Reserved Notes: 1. Typical measurements with an Si5326 at V 2. For all measurements: Vpk-pk on a single output, double the values for differential.

  • Page 109: Typical Scope Shots For Sfout Options

    Si53xx-RM 8.3. Typical Scope Shots for SFOUT Options Figure 46. sfout_2, CMOS Figure 47. sfout_3, lowSwingLVDS Rev. 0.52...

  • Page 110: Figure 48. Sfout_5, Lvpecl

    Si53xx-RM Figure 48. sfout_5, LVPECL Figure 49. sfout_6, CML Rev. 0.52...

  • Page 111: Figure 50. Sfout_7, Lvds

    Si53xx-RM Figure 50. sfout_7, LVDS Rev. 0.52...

  • Page 112: Crystal/Reference Clock Interfaces (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, And Si5375)

    Si5366, Si5368, Si5369, Si5374, and Si5375) All devices other than the Si5374 and Si5375 can use an external crystal or external clock as a reference. The Si5374 and Si5375 are limited to an external reference oscillator and cannot use a crystal. If an external clock is used, it must be ac coupled.

  • Page 113: Figure 53. Differential External Reference Input Example

    LVDS, LVPECL, CML, etc. Figure 53. Differential External Reference Input Example LVDS, LVPECL, CML, etc. Figure 54. Differential OSC Reference Input Example for Si5374 and Si5375 0.01 F  0.01 F (Not for Si5374 or Si5375) 0.01 F OSC-P 100  OSC-N 0.01 F Rev.

  • Page 114: Three-Level (3L) Input Pins (No External Resistors)

    Si53xx-RM 8.5. Three-Level (3L) Input Pins (No External Resistors) External Driver Parameter Input Voltage Low Input Voltage Mid Input Voltage High Input Low Current Input Mid Current Input High Current Note: The above currents are the amount of leakage that the 3L inputs can tolerate from an external driver. Si53xx 75 k...

  • Page 115: Three-Level (3L) Input Pins (With External Resistors)

    8.6. Three-Level (3L) Input Pins (With External Resistors) External Driver One of eight resistors from a Panasonic EXB-D10C183J (or similar) resistor pack Parameter Input Low Current Input Mid Current Input High Current Note: The above currents are the amount of leakage that the 3L inputs can tolerate from an external driver.

  • Page 116: Power Supply

    Si53xx-RM 9. Power Supply These devices incorporate an on-chip voltage regulator to power the device from supply voltages of 1.8, 2.5, or 3.3 V. Internal core circuitry is driven from the output of this regulator while I/O circuitry uses the external supply voltage directly.

  • Page 117: Packages And Ordering Guide

    Si53xx-RM 10. Packages and Ordering Guide Refer to the respective data sheet for your device packaging and ordering information. Rev. 0.52...

  • Page 118: Appendix A-Narrowband References

    Vectron VXM7-1074-114M285000 Note: See the manufacturer’s data sheets for detailed specifications for each crystal. Table 60. XA/XB Reference Sources and Frequencies RATE[1:0] NB/WB No crystal or external clock External clock Third overtone crystal External clock Fundamental mode crystal EFERENCES Table 59. Approved Crystals Website http://www.abracon.com...
  • Page 119 Si53xx-RM In some applications, a crystal with frequencies other than 114.285 MHz may be used. See “AN591: Crystal Selection for the Si5315, Si5317, and other Si53xx Any-Frequency Jitter Attenuating Clocks” for details and a current list of crystal vendors and approved part numbers. External reference (and crystal) frequency values should be avoided that result in an output frequency that is an integer or near integer multiple of the reference frequency.

  • Page 120: Figure 59. Typical Reference Jitter Transfer Function

    Si53xx-RM 38.88MHz XO, 38.88MHz CKIN, 38.88MHz CKOUT Figure 59. Typical Reference Jitter Transfer Function 1000 10000 100000 1000000 Frequency (Hz) Rev. 0.52 Jitter Xfer...

  • Page 121: Appendix B-Frequency Plans And Jitter Performance (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, Si5375)

    2 kHz minimum up to 2 MHz maximum. The two main causes of a low f3 are a low clock input frequency (which establishes an upper bound on f3) and a PLL multiplier ratio that is comprised of large and mutually prime nominators and denominators.

  • Page 122: Figure 61. Jitter Vs. F3 With Fpga

    Note that 38.88 MHz x 5 = 194.4 MHz. In this case, an FPGA was used to multiply a 38.88 MHz input clock up by a factor of five to 194.4 MHz, using a feature such as the Xilinx DCM (Digital Clock Manager).

  • Page 123: Figure 62. Reference Vs. Output Frequency

    Reference vs. Output Frequency Because of internal coupling, output frequencies that are an integer multiple (or close to an integer multiple) of the XA/XB reference frequency (either internal or external) should be avoided. Figure 62 illustrates this by showing a 38.88 MHz reference being used to generate both a 622.08 MHz output (which is an integer multiple of 38.88 MHz) and 696.399 MHz (which is not an integer multiple of 38.88 MHz).

  • Page 124: Figure 63. 622.08 Mhz Output With A 114.285 Mhz Crystal

    When selecting a reference frequency, with all other things being equal, the higher the reference frequency, the lower the output jitter. Figures 63 and 64 compare the results with a 114.285 MHz crystal versus a 40 MHz crystal. For a discussion of the available reference frequencies, see section " Resonator/External Clock Selection" on page 118.

  • Page 125: Figure 64. 622.08 Mhz Output With A 40 Mhz Crystal

    Figure 64. 622.08 MHz Output with a 40 MHz Crystal Jitter Band SONET_OC48, 12 kHz to 20 MHz SONET_OC192_A, 20 kHz to 80 MHz SONET_OC192_B, 4 to 80 MHz SONET_OC192_C, 50 kHz to 80 MHz Brick Wall_800 Hz to 80 MHz *Note: Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass (–60 dB/Dec) roll-offs per Telcordia GR-253-CORE.

  • Page 126: Appendix C-Typical Phase Noise Plots

    RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is below the loop bandwidth of the Any-Frequency device is caused by the jitter of the input clock, not the Any- Frequency Precision Clock.

  • Page 127: Figure 66. 155.52 Mhz In; 622.08 Mhz Out; Loop Bw = 7 Hz, Si5324

    Si53xx-RM Figure 66. 155.52 MHz In; 622.08 MHz Out; Loop BW = 7 Hz, Si5324 Rev. 0.52...

  • Page 128: Figure 67. 19.44 Mhz In; 156.25 Mhz Out; Loop Bw = 80 Hz

    Si53xx-RM Figure 67. 19.44 MHz In; 156.25 MHz Out; Loop BW = 80 Hz Rev. 0.52...

  • Page 129: Figure 68. 19.44 Mhz In; 156.25 Mhz Out; Loop Bw = 5 Hz, Si5324

    Si53xx-RM Figure 68. 19.44 MHz In; 156.25 MHz Out; Loop BW = 5 Hz, Si5324 Rev. 0.52...

  • Page 130: Figure 69. 27 Mhz In; 148.35 Mhz Out; Light Trace Bw = 6 Hz; Dark Trace Bw = 110 Hz, Si5324

    Si53xx-RM Figure 69. 27 MHz In; 148.35 MHz Out; Light Trace BW = 6 Hz; Dark Trace BW = 110 Hz, Si5324 Rev. 0.52...

  • Page 131: Figure 70. 61.44 Mhz In; 491.52 Mhz Out; Loop Bw = 7 Hz, Si5324

    Si53xx-RM Figure 70. 61.44 MHz In; 491.52 MHz Out; Loop BW = 7 Hz, Si5324 Rev. 0.52...

  • Page 132: Figure 71. 622.08 Mhz In; 672.16 Mhz Out; Loop Bw = 6.9 Khz

    Si53xx-RM Figure 71. 622.08 MHz In; 672.16 MHz Out; Loop BW = 6.9 kHz Rev. 0.52...

  • Page 133: Figure 72. 622.08 Mhz In; 672.16 Mhz Out; Loop Bw = 100 Hz

    Si53xx-RM Figure 72. 622.08 MHz In; 672.16 MHz Out; Loop BW = 100 Hz Rev. 0.52...

  • Page 134: Figure 73. 156.25 Mhz In; 155.52 Mhz Out

    Si53xx-RM Figure 73. 156.25 MHz In; 155.52 MHz Out Rev. 0.52...

  • Page 135: Figure 74. 78.125 Mhz In; 644.531 Mhz Out

    Figure 74. 78.125 MHz In; 644.531 MHz Out Table 63. Jitter Values for Figure 74 Jitter Bandwidth Broadband, 1 kHz to 10 MHz OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz OC-192, 50 kHz to 80 MHz Broadband, 800 Hz to 80 MHz Rev.

  • Page 136: Figure 75. 78.125 Mhz In; 690.569 Mhz Out

    Si53xx-RM Figure 75. 78.125 MHz In; 690.569 MHz Out Jitter Bandwidth Broadband, 1 kHz to 10 MHz OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz OC-192, 50 kHz to 80 MHz Broadband, 800 Hz to 80 MHz Table 64.

  • Page 137: Figure 76. 78.125 Mhz In; 693.493 Mhz Out

    Figure 76. 78.125 MHz In; 693.493 MHz Out Table 65. Jitter Values for Figure 76 Jitter Bandwidth Broadband, 1 kHz to 10 MHz OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz OC-192, 50 kHz to 80 MHz Broadband, 800 Hz to 80 MHz Rev.

  • Page 138: Figure 77. 86.685 Mhz In; 173.371 Mhz And 693.493 Mhz Out

    Si53xx-RM 86.685 MHz in, 173.371 MHz and 693.493 MHz out 0.00E+00 -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+02 1.00E+03 Red = 693.493 MHz Figure 77. 86.685 MHz In; 173.371 MHz and 693.493 MHz Out Jitter Bandwidth Broadband, 1 kHz to 10 MHz OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz...

  • Page 139: Figure 78. 86.685 Mhz In; 173.371 Mhz Out

    Si53xx-RM Figure 78. 86.685 MHz In; 173.371 MHz Out Rev. 0.52...

  • Page 140: Figure 79. 86.685 Mhz In; 693.493 Mhz Out

    Si53xx-RM Figure 79. 86.685 MHz In; 693.493 MHz Out Rev. 0.52...

  • Page 141: Figure 80. 155.52 Mhz And 156.25 Mhz In; 622.08 Mhz Out

    155.52 MHz and 156.25MHz in, 622.08 MHz out 0.00E+00 -2.00E+01 -4.00E+01 -6.00E+01 6.00E 01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 1.00E+02 1.00E+03 Blue = 155.52 MHz Figure 80. 155.52 MHz and 156.25 MHz In; 622.08 MHz Out Table 67. Jitter Values for Figure 80 Jitter Bandwidth Broadband, 100 Hz to 10 MHz OC-48, 12 kHz to 20 MHz...

  • Page 142: Figure 81. 10 Mhz In; 1 Ghz Out

    Si53xx-RM Figure 81. 10 MHz In; 1 GHz Out Rev. 0.52...
  • Page 143 Digital Video (HD-SDI) -100 -120 -140 -160 Brick Wall, 10 Hz to 20 MHz Peak-to-peak Phase noise equipment: Agilent model JS500. 27 MHz in, 148.5 MHz out 1000 10000 100000 1000000 Offset Frequency (Hz) Jitter Band 2.42 ps, RMS 14.0 ps Rev.

  • Page 144: Appendix D-Alarm Structure

    Si53xx-RM D—A PPENDIX LARM LOSX_INT LOSX_FLG Sticky LOSX_MSK Write 0 to clear LOS1_INT LOS1_FLG Sticky LOS1_MSK Write 0 to clear LOS2_INT LOS2_FLG Sticky LOS2_MSK Write 0 to clear FOS1_INT FOS1_FLG Sticky FOS1_MSK Write 0 to clear FOS2_INT FOS2_FLG Sticky FOS2_MSK Write 0 to clear LOL_INT...

  • Page 145: Figure 83. Si5368 And Si5369 Alarm Diagram (1 Of 2)

    /26;B,17 /26;B)/* Sticky /26;B06. Write 0 to clear /26B)/* /26B,17 Sticky /26B06. Write 0 to clear /26B)/* /26B,17 Sticky /26B06. Write 0 to clear /26B,17 /26B)/* Sticky /26B06. Write 0 to clear /26B)/* /26B,17 Sticky /26B06. Write 0 to clear )26B)/* )26B,17 Sticky...

  • Page 146: Figure 84. Si5368 And Si5369 Alarm Diagram (2 Of 2)

    Si53xx-RM /26B(1 CKIN3 Detector 3'B&. Detector )26B(1 /26,B(1 CKIN1 Detector 3'B&. Detector )26,B(1 /26B(1 CKIN2 Detector 3'B&. Detector )26B(1 Figure 84. Si5368 and Si5369 Alarm Diagram (2 of 2) /26B,17 )26B(1 /26B,17 )26B(1 &.B&21),*B5(* )6<1&B6:7&+B5(* )6<1&B6:,7&+B5(* LV DOZD\V KLJK IRU DQ 6L /26B,17 /26B,17 )26B(1...

  • Page 147: Appendix E-Internal Pullup, Pulldown By Pin

    E—I PPENDIX NTERNAL Tables 68–79 show which 2-Level CMOS pins have pullups or pulldowns. Note the value of the pullup/pulldown resistor is typically 75 k. ULLUP ULLDOWN BY Table 68. Si5316 Pullup/Down Pin # Si5316 Pull? RATE0 U, D DBL2_BY U, D RATE1 U, D...

  • Page 148: Table 71. Si5319, Si5324, Pullup/Down

    Si53xx-RM Table 71. Si5319, Si5324, Pullup/Down Table 70. Si5323 Pullup/Down Pin # Si5323 Pull? FRQTBL U, D AUTOSEL U, D RATE0 U, D DBL2_BY U, D RATE1 U, D CS_CA U, D BWSEL0 U, D BWSEL1 U, D FRQSEL0 U, D...

  • Page 149: Table 72. Si5325 Pullup/Down

    Table 72. Si5325 Pullup/Down Pin # Si5325 Pull? CS_CA U, D A2_SS CMODE U, D Table 73. Si5326 Pullup/Down Pin # Si5326 Pull? RATE0 U, D RATE1 U, D CS_CA U, D A2_SS CMODE U, D Rev. 0.52 Si53xx-RM...

  • Page 150: Table 74. Si5327 Pullup/Down

    Si53xx-RM Table 74. Si5327 Pullup/Down Pin # Si5327 Pull? RATE0 U, D RATE1 U, D U, D A2_SS CMODE U, D Table 75. Si5365 Pullup/Down Pin # Si5365 Pull? FRQTBL U, D CS0_C3A AUTOSEL U, D DBL2_BY U, D DSBL5 U, D CS1_C4A U, D...

  • Page 151: Table 76. Si5366 Pullup/Down

    Table 76. Si5366 Pullup/Down Pin # Si5366 Pull? FRQTBL U, D CS0_C3A FS_SW FS_ALIGN AUTOSEL U, D RATE0 U, D DBL2_BY U, D RATE1 U, D DBL_FS U, D CK_CONF FOS_CTL U, D CS1_C4A U, D BWSEL0 U, D BWSEL1 U, D DIV34_0 U, D...

  • Page 152: Table 77. Si5367 Pullup/Down

    Si53xx-RM Table 77. Si5367 Pullup/Down Pin # Si5367 Pull? CS0_C3A CS1_C4A U, D A2_SSB CMODE U, D Table 78. Si5368 Pullup/Down Pin # Si5368 Pull? CS0_C3A FS_ALIGN RATE0 U, D RATE1 U, D CS1_C4A U, D A2_SSB CMODE U, D Rev.

  • Page 153: Table 80. Si5374/75 Pullup/Down

    Table 79. Si5369 Pullup/Down Pin # Si5368 Pull? CS0_C3A FS_ALIGN RATE0 U, D RATE1 U, D CS1_C4A U, D A2_SSB CMODE U, D Table 80. Si5374/75 Pullup/Down Pin # Si5374/75 Pull? RSTL_A RSTL_B RSTL_C RSTL_D CS_CA_A CS_CA_B CS_CA_C CS_CA_A Rev. 0.52 Si53xx-RM...

  • Page 154: Output Format Jitter

    Si53xx-RM F—T PPENDIX YPICAL ROSSTALK UTPUT This appendix is divided into the following four sections:  Bypass Mode Performance  Power Supply Noise Rejection  Crosstalk  Output Format Jitter Bypass: 622.08 MHz In, 622.08 MHz Out -100 -110 -120 -130 -140 -150...
  • Page 155 Power Supply Noise Rejection Power Supply Noise to Output Transfer Function -100 -105 38.88 MHz in, 155.52 MHz out; Bandwidth = 110 Hz Rev. 0.52 Si53xx-RM 1000...
  • Page 156 Measurement conditions: 1. Using Si5365/66-EVB. 2. Clock input on CKIN1, a 0dBm sine wave from Rohde and Schwarz RF Generator, model SML03 3. Crosstalk interfering signal applied to CKIN3, a PECL output at 155.52 MHz 4. All differential, AC coupled signals 155.521 MHz in,...
  • Page 157 Clock Input Crosstalk: Phase Noise Plots 1 5 5 . 5 2 1 M H z in , 6 2 2 .0 8 4 M H z o u t -2 0 -4 0 -6 0 -8 0 - 1 0 0...
  • Page 158 Si53xx-RM Clock Input Crosstalk: Detail View -100 -110 -120 -130 Dark blue — No crosstalk Light blue — With crosstalk, low bandwidth Yellow — With crosstalk, high bandwidth Red — With crosstalk, in digital hold 155 .521 MH z i n, 622 .084 MH z ou t...
  • Page 159 Clock Input Crosstalk: Wideband Comparison -100 -120 -140 -160 -180 1000 Dark blue — Bandwidth = 6.72 kHz; no Xtalk Light blue — Bandwidth = 6.72 kHz; with Xtalk Jitter Band OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz Broadband, 800 Hz to 80 MHz 155 .521 M H z in , 62 2.08 4 M H z o u t...
  • Page 160 Si53xx-RM Clock Input Crosstalk: Output of Rohde and Schwartz RF -100 -110 -120 R ohde and S chwarz : 155.521 M H z O ffse t Fre q ue n cy (Hz) Rev. 0.52 1000...

  • Page 161: Table 81. Output Format Vs. Jitter

    Jitter vs. Output Format: 19.44 MHz In, 622.08 MHz Out -1 00 -1 20 -1 40 -1 60 10 0 100 0 Spectrum Analyzer: Agilent Model E444OA Bandwidth Broadband, 1 kHz to 10 MHz OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz OC-192, 50 kHz to 80 MHz...

  • Page 162: Appendix G-Near Integer Ratios

    Si53xx-RM G—N PPENDIX NTEGER To provide more details and to provide boundaries with respect to the “Reference vs. Output Frequency” issue described in Appendix B on page 121, the following study was performed and is presented below. Test Conditions  XA/XB External Reference held constant at 38.88 MHz ...

  • Page 163: Figure 86. ±200 Ppm, 10 Ppm Steps

    38.88 MHz External XA-XB Reference 1200 1000 155.49 155.5 155.51 Input Frequency Variation = ±200 ppm Figure 86. ±200 ppm, 10 ppm Steps 38.88 MHz External XA-XB Reference 1200 1000 155.2 155.3 155.3 155.4 155.4 155.5 155.5 155.6 155.6 155.7 155.7 155.8 155.8 155.9 155.9 Input Frequency Variation = ±2000 ppm Figure 87.

  • Page 164: Appendix H-Jitter Attenuation And Loop Bw

    Si53xx-RM H—J PPENDIX ITTER The following illustrates the effects of different loop BW values on the jitter attenuation of the Any-Frequency devices. The jitter consists of sine wave modulation at varying frequencies. The RMS jitter values of the modulated sine wave input is compared to the output jitter of an Si5326 and an Si5324. For reference, the top entry in the table lists the jitter without any modulation.

  • Page 165: Figure 88. Rf Generator, Si5326, Si5324; No Jitter (For Reference)

    0.00E+00 -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 Blue = RF Generator Figure 88. RF Generator, Si5326, Si5324; No Jitter (For Reference) 0.00E+00 -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08...

  • Page 166: Figure 90. Rf Generator, Si5326, Si5324 (100 Hz Jitter)

    Si53xx-RM 0.00E+00 -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 Blue = RF Generator Figure 90. RF Generator, Si5326, Si5324 (100 Hz Jitter) 0.00E+00 -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+02...

  • Page 167: Figure 92. Rf Generator, Si5326, Si5324 (1 Khz Jitter)

    0.00E+00 -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+02 1.00E+03 Blue = RF Generator Figure 92. RF Generator, Si5326, Si5324 (1 kHz Jitter) 0.00E+00 -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+02 1.00E+03 Blue = RF Generator Figure 93.

  • Page 168: Figure 94. Rf Generator, Si5326, Si5324 (10 Khz Jitter)

    Si53xx-RM 0.00E+00 -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+02 1.00E+03 Blue = RF Generator Figure 94. RF Generator, Si5326, Si5324 (10 kHz Jitter) 622.08 MHz in, 622.08 MHz out 1.00E+04 1.00E+05 1.00E+06 Offset Frequency (Hz) Green = Si5326 Rev.

  • Page 169: Appendix I-Si5374 And Si5375 Pcb Layout Recommendations

     Use a solid and undisturbed ground plane for the Si537x and all of the clock input and output return paths.  For applications that wish to logically connect the four RSTL_x signals, do not tie them together underneath the BGA package.

  • Page 170: Figure 96. Ground Plane And Reset

    Si53xx-RM These four resistors force the common RESET connection away from the BGA footprint Figure 96. Ground Plane and Reset RSTL_x Pins It is highly recommended that the four RSTL_x pins (RSTL_A, RSTL_B, RSTL_C and RSTL_D) be logically connected to one another so that the four DSPLLs are always either all in reset or are all out of reset. While in reset, the DSPLLs VCO will continue to run, and, because the VCOs will not be locked to any signal, they will drift and can be any frequency value within the VCO range.

  • Page 171: Figure 97. Output Clock Routing

    EVB (evaluation board) layout. For more details about this board, please refer to the Si537x-EVB Evaluation Board User's Guide. As much as is possible, do not route clock input and output signals underneath the BGA package. The clock output signals should go directly outwards from the BGA footprint.

  • Page 172: Figure 98. Osc_P, Osc_N Routing

    Si53xx-RM Avoid placing the OCS_P and OSC_N signals on the same layer as the clock outputs.  Add  grounded guard traces surrounding the OSC_P and OSC_N signals. Figure 98. OSC_P, OSC_N Routing Rev. 0.52 OSC_P, OSC_N...

  • Page 173: Appendix J-Si5374 And Si5375 Crosstalk

    J—Si5374 PPENDIX While the four DSPLLs of the Si5374 and Si5375 are in close physical and electrical proximity to one another, crosstalk interference between the DSPLLs is minimal. The following measurements show typical performance levels that can be expected for the Si5374 and Si5375 when all four of their DSPLLs are operating at frequencies that are close in value to one another, but not exactly the same.

  • Page 174: Figure 99. Si5374, Si5375 Dspll A

    Si53xx-RM Figure 99. Si5374, Si5375 DSPLL A Rev. 0.52...

  • Page 175: Figure 100. Si5374, Si5375 Dspll B

    Si53xx-RM Figure 100. Si5374, Si5375 DSPLL B Rev. 0.52...

  • Page 176: Figure 101. Si5374, Si5375 Dspll C

    Si53xx-RM Figure 101. Si5374, Si5375 DSPLL C Rev. 0.52...

  • Page 177: Figure 102. Si5374, Si5375 Dspll D

    DSPLLs that are next to one another will not have the same VCO value. For example, there are two possible VCO values for a 622.08 MHz clock output frequency. In this case, DSPLLs A and C would have one VCO value, while DSPLLs B and D would have a different VCO value.

  • Page 178: Figure 103

    Si53xx-RM Si5374/75 Register Map Partition Example In a typical line card application, an Si5374/75 will supply four clocks to four different channels that might need to support any combination of services. For example, say that each of the four DSPLLs (A, B, C or D) can be programmed for either a SONET, OTN/OTU or Ethernet frequency plan in any combination.

  • Page 179: Figure 104

    Suggested Ethernet SONET Ethernet OTN/OTU Figure 104. Rev. 0.52 Si53xx-RM recommended...

  • Page 180: Appendix K-Jitter Transfer And Peaking

    ITTER The follow set of curves show the jitter transfer versus frequency with a loop bandwidth value of 60 Hz. The clock input and output frequencies were both 10.24 MHz. The four curves all use the same data but are graphed at different scales to illustrate typical gain vs.

  • Page 181: Figure 106. Zoomed View Of Jitter Transfer

    2.000 0.000 -2.000 -4.000 -6.000 -8.000 -10.000 Figure 106. Zoomed View of Jitter Transfer 0.500 0.000 -0.500 -1.000 -1.500 -2.000 Figure 107. Zoomed Again View of Jitter Transfer (Showing Peaking) Jitter Transfer Offset Frequency, Hz Jitter Transfer Offset Frequency, Hz Rev.

  • Page 182: Figure 108. Maximum Zoomed View Of Jitter Peaking

    Si53xx-RM 0.100 0.050 0.000 -0.050 -0.100 -0.150 -0.200 Figure 108. Maximum Zoomed View of Jitter Peaking Jitter Transfer Offset Frequency, Hz Rev. 0.52...

  • Page 183: Document Change List

    3.3 V).” Revision 0.42 to Revision 0.5  Added Si5327, Si5369, Si5374, and Si5375.  Removed Si5319 and Si5323 from the spec tables.  Updated the typical phase noise plots.  Added new appendixes G, H, I, and J. ...

  • Page 184: Contact Information

    Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur.

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