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2
I
C - P
R O GRA MM A B LE
G
EN ERA TO R
Features
Generates up to 8 non-integer-related
frequencies from 8 kHz to 160 MHz
2
I
C user definable configuration
Exact frequency synthesis at each output
(0 ppm error)
Highly linear VCXO
Optional clock input (CLKIN)
Low output period jitter: 100 ps pp
Configurable spread spectrum selectable
at each output
Operates from a low-cost, fixed frequency
crystal: 25 or 27 MHz
Supports static phase offset
Programmable rise/fall time control
Applications
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Description
2
The Si5351 is an I
C configurable clock generator that is ideally suited for replacing
crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in
cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional
divider architecture, the Si5351 can generate any frequency up to 160 MHz on each of its
outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide
variety of applications. The Si5351A generates up to 8 free-running clocks using an
internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an
internal VCXO and provides the flexibility to replace both free-running clocks and
synchronous clocks. The Si5351B eliminates the need for higher cost, custom pullable
crystals while providing reliable operation over a wide tuning range. The Si5351C offers
the same flexibility but synchronizes to an external reference clock (CLKIN).
Functional Block Diagram
XA
OSC
XB
2
I
C
SSEN
OEB
N = 2 or 7
Preliminary Rev. 0.95 8/11
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
A
NY
+ VCXO
Glitchless frequency changes
Separate voltage supply pins:
Core VDD: 2.5 or 3.3 V
Output VDDO: 1.8, 2.5, or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
Adjustable output-output delay
Available in 3 packages types:
10-MSOP: 3 outputs
24-QSOP: 8 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compliant
Supports HCSL compatible swing
Residential gateways
Networking/communication
Servers, storage
XO replacement
XA
Multi
PLLA
Synth
0
Multi
Synth
1
XB
PLLB
VC
Multi
Synth
N
Si5351A
2
I
C
SSEN
OEB
Copyright © 2011 by Silicon Laboratories
S i 5 3 5 1 A / B / C
- F
R E Q U E N C Y
Multi
Synth
0
OSC
PLL
Multi
Synth
1
Multi
Synth
VCXO
2
CLKIN
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
Multi
Synth
7
Si5351B
CMOS C
L O C K
10-MSOP
24-QSOP
20-QFN
Ordering Information:
See page 66
XA
Multi
Synth
0
OSC
PLLA
Multi
Synth
XB
1
Multi
Synth
PLLB
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
2
I
C
Multi
Synth
7
INTR
OEB
Si5351C
Si5351A/B/C
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Table of Contents
Related Manuals for Silicon Laboratories SI5351A/B/C
Summary of Contents for Silicon Laboratories SI5351A/B/C
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Page 1: Functional Block Diagram
Synth Multi Synth Multi Synth Multi Synth SSEN Si5351B Copyright © 2011 by Silicon Laboratories S i 5 3 5 1 A / B / C CMOS C L O C K 10-MSOP 24-QSOP 20-QFN Ordering Information: See page 66... - Page 2 Si5351A/B/C Preliminary Rev. 0.95...
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Page 3: Table Of Contents
Contact Information ............72 Preliminary Rev. 0.95 Si5351A/B/C Page... -
Page 4: Electrical Specifications
Si5351A/B/C 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Ambient Temperature Core Supply Voltage Output Buffer Voltage DDOx Notes:All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. - Page 5 Down spread Center spread Vc = 10–90% of V Vc = 10–90% of V = 3.3 V* = –40 to 85 °C) Test Condition –0.1 0.7 x V Preliminary Rev. 0.95 Si5351A/B/C Unit — — — µs — — ps/step –0.1 —...
- Page 6 Si5351A/B/C Table 5. Output Clock Characteristics = 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C) Parameter Symbol Frequency Range Load Capacitance Duty Cycle Rise/Fall Time Output High Voltage Output Low Voltage Period Jitter Period Jitter VCXO...
- Page 7 — DDI2C Test Condition Package 10-MSOP Still Air 24-QSOP 20-QFN 10-MSOP Still Air 24-QSOP 20-QFN Preliminary Rev. 0.95 Si5351A/B/C Fast Mode Unit 400 kbps –0.5 0.3 x V DDI2C 0.7 x V 3.63 DDI2C — 0.2 x V DDI2C –10 µA...
- Page 8 Si5351A/B/C Table 9. Absolute Maximum Ratings Parameter DC Supply Voltage Input Voltage Junction Temperature Soldering Temperature (Pb-free profile) Soldering Temperature Time at TPEAK (Pb-free profile) Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet.
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Page 9: Detailed Block Diagrams
Figure 1. Block Diagrams of 3-Output and 8-Output Si5351A Devices Si5351A 3-Output MultiSynth MultiSynth MultiSynth Si5351A 8-Output MultiSynth MultiSynth MultiSynth MultiSynth MultiSynth MultiSynth MultiSynth MultiSynth 20-QFN, 24-QSOP Preliminary Rev. 0.95 Si5351A/B/C VDDO CLK0 CLK1 CLK2 10-MSOP VDDOA CLK0 CLK1 VDDOB CLK2 CLK3 VDDOC CLK4 CLK5 VDDOD... - Page 10 Si5351A/B/C Interface Control Logic SSEN CLKIN Interface INTR Control Logic Figure 2. Block Diagrams of Si5351B and Si5351C 8-Output Devices Si5351B MultiSynth MultiSynth MultiSynth VCXO MultiSynth MultiSynth MultiSynth MultiSynth MultiSynth 20-QFN, 24-QSOP Si5351C MultiSynth MultiSynth MultiSynth MultiSynth MultiSynth MultiSynth MultiSynth...
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Page 11: Functional Description
Multi Synth Figure 3. Si5351 Block Diagram Selectable internal Optional load capacitors Additional external 6 pF, 8 pF, 10 pF load capacitors (< 2 pF) Preliminary Rev. 0.95 Si5351A/B/C Output Stage VDDOA CLK0 CLK1 VDDOB CLK2 CLK3 VDDOC CLK4 CLK5... -
Page 12: Synthesis Stages
Si5351A/B/C 3.1.2. External Clock Input (CLKIN) The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs. CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL input frequency to 30 MHz. -
Page 13: Spread Spectrum
Si5351A/B/C 3.4. Spread Spectrum Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its frequency, which effectively reduces the overall amplitude of its radiated energy. See “AN554: Si5350/51 PCB Layout Guide”... -
Page 14: I2C Interface
Si5351A/B/C 4. I C Interface Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the C interface. The following is a list of the common features that are controllable through the I summary of register functions is shown in Section 7. -
Page 15: Write Operation
0 – Write A – Acknowledge (SDA LOW) N – Not Acknowledge (SDA HIGH) S – START condition P – STOP condition Figure 10. I C Read Operation C-Bus Standard. SDA timeout is supported for compatibility Preliminary Rev. 0.95 Si5351A/B/C... -
Page 16: Configuring The Si5351
Si5351A/B/C 5. Configuring the Si5351 The Si5351 is a highly flexible clock generator which is entirely configurable through its I C interface. The device’s default configuration is stored in non-volatile memory (NVM) as shown in Figure 11. The NVM is a one time programmable memory (OTP) which can store a custom user configuration at power-up. - Page 17 Si5351A/B/C Disable Outputs Set CLKx_DIS high; Reg. 3 = 0xFF Powerdown all output drivers Reg. 16, 17, 18, 19, 20, 21, 22, 23 = 0x80 Set interrupt masks (see register 2 description) Write new configuration to device using Register the contents of the register map generated by ClockBuilder Desktop.
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Page 18: Si5351 Application Examples
Si5351A/B/C 5.2. Si5351 Application Examples The Si5351 is a versatile clock generator which serves a wide variety of applications. The following examples show how it can be used to replace crystals, crystal oscillators, VCXOs, and PLLs. 5.3. Replacing Crystals and Crystal Oscillators Using an inexpensive external crystal, the Si5351A can generate up to 8 different free-running clock frequencies for replacing crystals and crystal oscillators. -
Page 19: Replacing Crystals, Crystal Oscillators, And Vcxos
48 MHz Synth CLK2 Multi 28.322 MHz Synth CLK3 Multi 74.25 MHz Synth CLK4 Multi 74.25/1.001 MHz Synth CLK5 Multi 24.576 MHz Synth Synchronous Clocks Preliminary Rev. 0.95 Si5351A/B/C Ethernet Controller HDMI Port Video/Audio Processor Ethernet Controller HDMI Port Video/Audio Processor... -
Page 20: Replacing A Crystal With A Clock
Si5351A/B/C 5.6. Replacing a Crystal with a Clock The Si5351 can be driven with a clock signal through the XA input pin. Note: Float the XB input while driving the XA input with a clock Figure 16. Si5351 Driven by a Clock Signal 5.7. -
Page 21: Design Considerations
Si5351A/B/C 6. Design Considerations The Si5351 is a self-contained clock generator that requires very few external components. The following general guidelines are recommended to ensure optimum performance. Refer to “AN554: Si5350/51 PCB Layout Guide” for additional layout recommendations. 6.1. Power Supply Decoupling/Filtering The Si5351 has built-in power supply filtering circuitry and extensive internal Low Drop Out (LDO) voltage regulators to help minimize the number of external bypass components. -
Page 22: Trace Characteristics
6.6. Trace Characteristics The Si5351A/B/C features various output current drives ranging from 2 to 8 mA (default). It is recommended to configure the trace characteristics as shown in Figure 18 when an output drive setting of 8 mA is used. -
Page 23: Register Map Summary
MS0_P1[15:8] MS0_P1[7:0] MS0_P2[15:8] MS0_P2[7:0] MS1_P3[15:8] MS1_P3[7:0] R1_DIV[2:0] MS1_P1[15:8] MS1_P1[7:0] MS1_P2[15:8] MS1_P2[7:0] MS2_P3[15:8] MS2_P3[7:0] R2_DIV[2:0] MS2_P1[15:8] MS2_P1[7:0] MS2_P2[15:8] MS2_P2[7:0] Preliminary Rev. 0.95 Si5351A/B/C REVID[1:0] CLK2_EN CLK1_EN CLK0_EN OEB_CLK2 OEB_CLK1 OEB_CLK0 PLLA_SRC CLK0_IDRV[1:0] CLK1_IDRV[1:0] CLK2_IDRV[1:0] CLK3_IDRV[1:0] CLK4_IDRV[1:0] CLK5_IDRV[1:0] CLK6_IDRV[1:0] CLK7_IDRV[1:0] CLK0_DIS_STATE CLK4_DIS_STATE... - Page 24 Si5351A/B/C Register MS3_P3[19:16] MS4_P3[19:16] MS5_P3[19:16] 93–164 PLL, MultiSynth, and output clock delay offset Configuration Registers. Use ClockBuilder Desktop Software to Determine These Register Values. 173–176 PLLB_RST 178–182 XTAL_CL 184–255 MS3_P3[15:8] MS3_P3[7:0] R3_DIV[2:0] MS3_P1[15:8] MS3_P1[7:0] MS3_P2[15:8] MS3_P2[7:0] MS4_P3[15:8] MS4_P3[7:0] R4_DIV[2:0] MS4_P1[15:8]...
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Page 25: Register Descriptions
0: Valid clock signal at the CLKIN pin. 1: Loss of signal detected at the CLKIN pin. Reserved Leave as default. REVID[1:0] Revision ID. Device revision number. Set at the factory. LOL_A Function Preliminary Rev. 0.95 Si5351A/B/C REVID[1:0] C interface until initialization is com-... - Page 26 Si5351A/B/C Register 1. Interrupt Status Sticky Name SYS_INIT_STKY LOL_B_STKY LOL_A_STKY LOS_STKY Type Reset value = 0000 0000 Name SYS_INIT_STKY System Calibration Status Sticky Bit. The SYS_INIT_STKY bit is triggered when the SYS_INIT bit (register 0, bit 7) is trig- gered high. It remains high until cleared. Writing a 0 to this register bit will cause it to clear.
- Page 27 CLKIN Loss Of Signal Mask (Si5351C Only). Use this mask bit to prevent the INTR pin (Si5351C only) from going low when LOS is asserted. 0: Do not mask the LOS interrupt. 1: Mask the LOS interrupt. Reserved Leave as default. Function Preliminary Rev. 0.95 Si5351A/B/C...
- Page 28 Si5351A/B/C Register 3. Output Enable Control Name CLK7_OEB CLK6_OEB CLK5_OEB CLK4_OEB CLK3_OEB CLK2_OEB CLK1_OEB CLK0_OEB Type Reset value = 0000 0000 Name CLKx_OEB Output Disable for CLKx. Where x = 0, 1, 2, 3, 4, 5, 6, 7 0: Enable CLKx output.
- Page 29 Input Source Select for PLLA. 0: Select the XTAL input as the reference clock for PLLA. 1: Select the CLKIN input as the reference clock for PLLA (Si5351C only). Reserved Leave as default. PLLB_SRC PLLA_SRC Function Preliminary Rev. 0.95 Si5351A/B/C...
- Page 30 Si5351A/B/C Register 16. CLK0 Control Name CLK0_PDN MS0_INT Type Reset value = 0000 0000 Name CLK0_PDN Clock 0 Power Down. This bit allows powering down the CLK0 output driver to conserve power when the out- put is unused. 0: CLK0 is powered up.
- Page 31 11: Select MultiSynth 0 as the source for CLK1. Select this option when using the Si5351 to generate free-running or synchronous clocks. CLK1_IDRV[1:0] CLK1 Output Rise and Fall time / Drive Strength Control. 00: 2 mA 01: 4 mA 10: 6 mA 11: 8 mA MS1_SRC CLK1_INV CLK1_SRC[1:0] Function Preliminary Rev. 0.95 Si5351A/B/C CLK1_IDRV[1:0]...
- Page 32 Si5351A/B/C Register 18. CLK2 Control Name CLK2_PDN MS2_INT Type Reset value = 0000 0000 Name CLK2_PDN Clock 2 Power Down. This bit allows powering down the CLK2 output driver to conserve power when the out- put is unused. 0: CLK2 is powered up.
- Page 33 These bits determine the input source for CLK3. CLK3_IDRV[1:0] CLK3 Output Rise and Fall time / Drive Strength Control. 00: 2 mA 01: 4 mA 10: 6 mA 11: 8 mA MS3_SRC CLK3_INV CLK3_SRC[1:0] Function Preliminary Rev. 0.95 Si5351A/B/C CLK3_IDRV[1:0]...
- Page 34 Si5351A/B/C Register 20. CLK4 Control Name CLK4_PDN MS4_INT Type Reset value = 0000 0000 Name CLK4_PDN Clock 4 Power Down. This bit allows powering down the CLK4 output driver to conserve power when the out- put is unused. 0: CLK4 is powered up.
- Page 35 11: Select MultiSynth 0 as the source for CLK5. Select this option when using the Si5351 to generate free-running or synchronous clocks. CLK5_IDRV[1:0] CLK5 Output Rise and Fall time / Drive Strength Control. 00: 2 mA 01: 4 mA 10: 6 mA 11: 8 mA MS5_SRC CLK5_INV CLK5_SRC[1:0] Function Preliminary Rev. 0.95 Si5351A/B/C CLK5_IDRV[1:0]...
- Page 36 Si5351A/B/C Register 22. CLK6 Control Name CLK6_PDN FBA_INT Type Reset value = 0000 0000 Name CLK6_PDN Clock 7 Power Down. This bit allows powering down the CLK6 output driver to conserve power when the out- put is unused. 0: CLK6 is powered up.
- Page 37 11: Select MultiSynth 0 as the source for CLK7. Select this option when using the Si5351 to generate free-running or synchronous clocks. CLK7_IDRV[1:0] CLK7 Output Rise and Fall time / Drive Strength Control. 00: 2 mA 01: 4 mA 10: 6 mA 11: 8 mA MS7_SRC CLK7_INV CLK7_SRC[1:0] Function Preliminary Rev. 0.95 Si5351A/B/C CLK7_IDRV[1:0]...
- Page 38 Si5351A/B/C Register 24. CLK3–0 Disable State Name CLK3_DIS_STATE Type Reset value = 0000 0000 Name CLKx_DIS_STATE Clock x Disable State. Where x = 0, 1, 2, 3. These 2 bits determine the state of the CLKx output when dis- abled. Individual output clocks can be disabled using register Output Enable Con- trol located at address 3.
- Page 39 Register 43. Multisynth0 Parameters Name Type Reset value = xxxx xxxx Name MS0_P3[7:0] Multisynth0 Parameter 3. This 20-bit number is an encoded representation of the denominator for the frac- tional part of the MultiSynth0 Divider. MS0_P3[15:8] Function MS0_P3[7:0] Function Preliminary Rev. 0.95 Si5351A/B/C...
- Page 40 Si5351A/B/C Register 44. Multisynth0 Parameters Name Type Reset value = xxxx xxxx Name Unused R0_DIV[2:0] R0 Output Divider. 000b: Divide by 1 001b: Divide by 2 010b: Divide by 4 011b: Divide by 8 100b: Divide by 16 101b: Divide by 32...
- Page 41 Name Type Reset value = xxxx xxxx Name MS0_P2[15:8] Multisynth0 Parameter 2. This 20-bit number is an encoded representation of the numerator for the fractional part of the MultiSynth1 Divider. MS0_P1[7:0] Function Function MS0_P2[15:8] Function Preliminary Rev. 0.95 Si5351A/B/C MS0_P2[19:16]...
- Page 42 Si5351A/B/C Register 49. Multisynth0 Parameters Name Type Reset value = xxxx xxxx Name MS0_P2[7:0] Multisynth0 Parameter 2. This 20-bit number is an encoded representation of the numerator for the fractional part of the MultiSynth1 Divider. Register 50. Multisynth1 Parameters Name...
- Page 43 Register 53. Multisynth1 Parameters Name Type Reset value = xxxx xxxx Name MS1_P1[15:8] Multisynth1 Parameter 1. This 18-bit number is an encoded representation of the integer part of the MultiSynth1 divider. R1_DIV[2:0] Function MS1_P1[15:8] Function Preliminary Rev. 0.95 Si5351A/B/C MS1_P1[17:16]...
- Page 44 Si5351A/B/C Register 54. Multisynth1 Parameters Name Type Reset value = xxxx xxxx Name MS1_P1[7:0] Multisynth1 Parameter 1. This 18-bit number is an encoded representation of the integer part of the MultiSynth1 divider. Register 55. Multisynth1 Parameters Name MS1_P3[19:16] Type Reset value = xxxx xxxx...
- Page 45 Type Reset value = xxxx xxxx Name MS1_P3[7:0] Multisynth1 Parameter 3. This 20-bit number is an encoded representation of the denominator for the frac- tional part of the MultiSynth1 divider. MS1_P2[7:0] Function MS1_P3[15:8] Function MS1_P3[7:0] Function Preliminary Rev. 0.95 Si5351A/B/C...
- Page 46 Si5351A/B/C Register 60. Multisynth2 Parameters Name Type Reset value = xxxx xxxx Name Unused R2_DIV[2:0] R2 Output Divider. 000b: Divide by 1 001b: Divide by 2 010b: Divide by 4 011b: Divide by 8 100b: Divide by 16 101b: Divide by 32...
- Page 47 Name Type Reset value = xxxx xxxx Name MS2_P2[15:8] Multisynth2 Parameter 2. This 20-bit number is an encoded representation of the numerator for the fractional part of the Multisynth2 divider. MS2_P1[7:0] Function Function MS2_P2[15:8] Function Preliminary Rev. 0.95 Si5351A/B/C MS2_P2[19:16]...
- Page 48 Si5351A/B/C Register 65. Multisynth2 Parameters Name Type Reset value = xxxx xxxx Name MS2_P2[7:0] Multisynth2 Parameter 2. This 20-bit number is an encoded representation of the numerator for the fractional part of the Multisynth2 divider. Register 66. Multisynth3 Parameters Name...
- Page 49 Register 69. Multisynth3 Parameters Name Type Reset value = xxxx xxxx Name MS3_P1[15:8] Multisynth3 Parameter 1. This 18-bit number is an encoded representation of the integer part of the Multisynth3 divider. R3_DIV[2:0] Function MS3_P1[15:8] Function Preliminary Rev. 0.95 Si5351A/B/C MS3_P1[17:16]...
- Page 50 Si5351A/B/C Register 70. Multisynth3 Parameters Name Type Reset value = xxxx xxxx Name MS3_P1[7:0] Multisynth3 Parameter 1. This 18-bit number is an encoded representation of the integer part of the Multisynth3 divider. Register 71. Multisynth3 Parameters Name MS3_P3[19:16] Type Reset value = xxxx xxxx...
- Page 51 Name Type Reset value = xxxx xxxx Name MS4_P3[7:0] Multisynth4 Parameter 3. This 20-bit number is an encoded representation of the numerator for the fractional part of the Multisynth4 divider. MS3_P2[7:0] Function MS4_P3[15:8] Function MS4_P3[7:0] Function Preliminary Rev. 0.95 Si5351A/B/C...
- Page 52 Si5351A/B/C Register 76. Multisynth4 Parameters Name Type Reset value = xxxx xxxx Name Unused R4_DIV[2:0] R4 Output Divider. 000b: Divide by 1 001b: Divide by 2 010b: Divide by 4 011b: Divide by 8 100b: Divide by 16 101b: Divide by 32...
- Page 53 Name Type Reset value = xxxx xxxx Name MS4_P2[15:8] Multisynth4 Parameter 2. This 20-bit number is an encoded representation of the numerator for the fractional part of the Multisynth4 Divider. MS4_P1[7:0] Function Function MS4_P2[15:8] Function Preliminary Rev. 0.95 Si5351A/B/C MS4_P2[19:16]...
- Page 54 Si5351A/B/C Register 81. Multisynth4 Parameters Name Type Reset value = xxxx xxxx Name MS4_P2[7:0] Multisynth4 Parameter 2. This 20-bit number is an encoded representation of the numerator for the fractional part of the Multisynth4 divider. Register 82. Multisynth5 Parameters Name...
- Page 55 Register 85. Multisynth5 Parameters Name Type Reset value = xxxx xxxx Name MS5_P1[15:8] Multisynth5 Parameter 1. This 18-bit number is an encoded representation of the integer part of the Multisynth5 divider. R5_DIV[2:0] Function MS5_P1[15:8] Function Preliminary Rev. 0.95 Si5351A/B/C MS5_P1[17:16]...
- Page 56 Si5351A/B/C Register 86. Multisynth5 Parameters Name Type Reset value = xxxx xxxx Name MS5_P1[7:0] Multisynth5 Parameter 1. This 18-bit number is an encoded representation of the integer part of the Multisynth5 divider. Register 87. Multisynth5 Parameters Name MS5_P3[19:16] Type Reset value = xxxx xxxx...
- Page 57 Multisynth7 Parameter 1. This 8-bit number is the Multisynth6 divide ratio. Multisynth6 divide ratio can only be even integers greater than or equal to 6. All other divide values are invalid. MS5_P2[7:0] Function MS6_P1[7:0] Function MS7_P1[7:0] Function Preliminary Rev. 0.95 Si5351A/B/C...
- Page 58 Si5351A/B/C Register 92. Clock 6 and 7 Output Divider Name Type Reset value = xxxx xxxx Name Reserved Leave as default. R7_DIV[2:0] R7 Output Divider. 000b: Divide by 1 001b: Divide by 2 010b: Divide by 4 011b: Divide by 8...
- Page 59 CLK2_PHOFF[6:0] Clock 2 Initial Phase Offset. CLK2_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where Tvco is the period of the VCO/PLL associated with this output. CLK0_PHOFF[6:0] Function CLK1_PHOFF[6:0] Function CLK2_PHOFF[6:0] Function Preliminary Rev. 0.95 Si5351A/B/C...
- Page 60 Si5351A/B/C Register 168. CLK3 Initial Phase Offset Name Type Reset value = 0000 0000 Name Reserved Only write 0 to this bit. CLK3_PHOFF[6:0] Clock 3 Initial Phase Offset. CLK3_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
- Page 61 Crystal Inputs (XA, XB)" on page 11. 00: Reserved. Do not select this option. 01: Internal CL = 6 pF. 10: Internal CL = 8 pF. 11: Internal CL = 10 pF (default). Reserved Leave as default. PLLA_RST Function Function Preliminary Rev. 0.95 Si5351A/B/C...
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Page 62: Si5351A Pin Descriptions (20-Pin Qfn, 24-Pin Qsop)
Si5351A/B/C 9. Si5351A Pin Descriptions (20-Pin QFN, 24-Pin QSOP) Si5351A 20-QFN Top View Pin Number Pin Name 20-QFN 24-QSOP CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 SSEN VDDOA VDDOB VDDOC VDDOD Center Pad 5, 8, 17, 19 1. I = Input, O = Output, P = Power. -
Page 63: Si5351B Pin Descriptions (20-Pin Qfn, 24-Pin Qsop)
Output voltage supply pin for CLK2 and CLK3. See 6.2 Output voltage supply pin for CLK4 and CLK5. See 6.2 Output voltage supply pin for CLK6 and CLK7. See 6.2 Ground Preliminary Rev. 0.95 Si5351A/B/C Si5351B 24-QSOP Top View CLK6 CLK7... -
Page 64: Si5351C Pin Descriptions (20-Pin Qfn, 24-Pin Qsop)
Si5351A/B/C 11. Si5351C Pin Descriptions (20-Pin QFN, 24-Pin QSOP) Si5351C 20-QFN Top View INTR Pin Number Pin Name 20-QFN 24-QSOP CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 INTR CLKIN VDDOA VDDOB VDDOC VDDOD Center Pad 5, 8, 17, 19 Notes: 1. -
Page 65: Si5351A Pin Descriptions (10-Pin Msop)
C bus. This pin must be pulled-up using a pull-up resistor of at least 1 k. Core voltage supply pin. Output voltage supply pin for CLK0, CLK1, and CLK2. See "6.2. Power Supply Sequencing" on page 21. Ground. Preliminary Rev. 0.95 Si5351A/B/C... -
Page 66: Ordering Information
Si5351A/B/C 13. Ordering Information Si5351X An evaluation kit containing ClockBuilder Desktop software and hardware enable easy evaluatin of the Si5351A/B/C. The orderable part numbers for the evaluation kits are provided in Figure 20. Si535X Figure 20. Si5351A/B/C Evaluation Kit *Note: The 10-MSOP is only available in the Si5351A variant. -
Page 67: Package Outline (24-Pin Qsop)
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. — — 0.10 — 0.19 — 0.15 — 8.55 8.65 6.00 BSC 3.81 3.90 0.635 BSC 0.40 — 0.25 BSC — 0.10 0.17 0.10 Preliminary Rev. 0.95 Si5351A/B/C 1.75 0.25 0.30 0.25 8.75 3.99 1.27... -
Page 68: Package Outline (20-Pin Qfn)
Si5351A/B/C 15. Package Outline (20-Pin QFN) Dimension Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. -
Page 69: Package Outline (10-Pin Msop)
0.85 0.17 — 0.08 — 3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.40 0.60 0.25 BSC — — — — — — — — — Preliminary Rev. 0.95 Si5351A/B/C 1.10 0.15 0.95 0.33 0.23 0.80 0.20 0.25 0.10 0.08... -
Page 70: Document Change List
Si5351A/B/C OCUMENT HANGE Revision 0.1 to Revision 0.9 Updated max output frequency. Updated kV values in Table 3 on page 5. Updated "3.4. Spread Spectrum" on page 13. Added "5.1. Writing a Custom Configuration to RAM"... - Page 71 Si5351A/B/C OTES Preliminary Rev. 0.95...
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Page 72: Contact Information
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