Functional Description; Input Stage - Silicon Laboratories SI5351A/B/C Product Manual

3. Functional Description

The Si5351 is a versatile I
oscillators, VCXOs, PLLs, and buffers. A block diagram showing the general architecture of the Si5351 is shown in
Figure 3. The device consists of an input stage, two synthesis stages, and an output stage.
The input stage accepts an external crystal (XTAL), a clock input (CLKIN), or a control voltage input (VC)
depending on the version of the device (A/B/C). The first stage of synthesis multiplies the input frequencies to an
high-frequency intermediate clock, while the second stage of synthesis uses high resolution MultiSynth fractional
dividers to generate the desired output frequencies. Additional integer division is provided at the output stage for
generating output frequencies as low as 8 kHz. Crosspoint switches at each of the synthesis stages allows total
flexibility in routing any of the inputs to any of the outputs.
Because of this high resolution and flexible synthesis architecture, the Si5351 is capable of generating
synchronous or free-running non-integer related clock frequencies at each of its outputs, enabling one device to
synthesize clocks for multiple clock domains in a design.
Input
Stage
CLKIN Div
XA
XTAL OSC
XB
VC
VCXO

3.1. Input Stage

3.1.1. Crystal Inputs (XA, XB)
The Si5351 uses a fixed-frequency standard AT-cut crystal as a reference to the internal oscillator. The output of
the oscillator can be used to provide a free-running reference to one or both of the PLLs for generating
asynchronous clocks. The output frequency of the oscillator will operate at the crystal frequency, either 25 MHz or
27 MHz. The crystal is also used as a reference to the VCXO to help maintain its frequency accuracy.
Internal load capacitors (C
to the Si5351. Options for internal load capacitors are 6, 8, or 10 pF. Crystals with alternate load capacitance
requirements are supported using additional external load capacitors as shown in Figure 4. Refer to application
note AN551 for crystal recommendations.
Figure 4. External XTAL with Optional Load Capacitors
2
C programmable clock generator that is ideally suited for replacing crystals, crystal
Synthesis
Stage 1
PLL A
(SSC)
PLL B
(VCXO)
Figure 3. Si5351 Block Diagram
) are provided to eliminate the need for external components when connecting a crystal
L
C
L XA
XB
C
L
Optional
Additional external
load capacitors
(< 2 pF)
Preliminary Rev. 0.95
Synthesis Output
Stage 2 Stage
Multi
Synth R0
0
Multi
Synth R1
1
Multi
Synth R2
2
Multi
Synth R3
3
Multi
Synth R4
4
Multi
Synth R5
5
Multi
Synth R6
6
Multi
Synth R7
7
Selectable internal
C C
L L
load capacitors
6 pF, 8 pF, 10 pF
Si5351A/B/C
VDDOA
CLK0
CLK1
VDDOB
CLK2
CLK3
VDDOC
CLK4
CLK5
VDDOD
CLK6
CLK7
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