Silicon laboratories SI5365 Generator Manuals

Table of Contents

3

Any-Frequency Precision Clock Product Family Overview

12

Wideband Devices

15

Narrowband Vs. Wideband Overview

15

Any-Frequency Clock Family Members

16

Si5316

16

Figure 1. Si5316 Any-Frequency Jitter Attenuator Block Diagram

16

Si5319

17

Figure 2. Si5319 Any-Frequency Jitter Attenuating Clock Multiplier Block Diagram

17

Si5322

18

Figure 3. Si5322 Low Jitter Clock Multiplier Block Diagram

18

Si5323

19

Figure 4. Si5323 Jitter Attenuating Clock Multiplier Block Diagram

19

Si5324

20

Figure 5. Si5324 Clock Multiplier and Jitter Attenuator Block Diagram

20

Si5325

21

Figure 6. Si5325 Low Jitter Clock Multiplier Block Diagram

21

Si5326

22

Figure 7. Si5326 Clock Multiplier and Jitter Attenuator Block Diagram

22

Si5327

23

Figure 8. Si5327 Clock Multiplier and Jitter Attenuator Block Diagram

23

Si5328

24

Figure 9. Si5328 Clock Multiplier and Jitter Attenuator Block Diagram

24

Si5365

25

Figure 10. Si5365 Low Jitter Clock Multiplier Block Diagram

25

Si5366

26

Figure 11. Si5366 Jitter Attenuating Clock Multiplier Block Diagram

26

Si5367

27

Figure 12. Si5367 Clock Multiplier Block Diagram

27

Si5368

28

Figure 13. Si5368 Clock Multiplier and Jitter Attenuator Block Diagram

28

Si5369

29

Si5374/75/76 Compared to Si5324/19/26

29

Figure 14. Si5369 Clock Multiplier and Jitter Attenuator Block Diagram

29

Si5374

30

Figure 15. Si5374 Functional Block Diagram

30

Si5375

31

Figure 16. Si5375 Functional Block Diagram

31

Si5376

32

Figure 17. Si5376 Functional Block Diagram

32

DSPLL (All Devices)

33

Figure 18. Any-Frequency Precision Clock DSPLL Block Diagram

33

Clock Multiplication

34

Figure 19. Clock Multiplication Circuit

34

PLL Performance

35

Jitter Generation

35

Jitter Transfer

35

Figure 20. PLL Jitter Transfer Mask/Template

35

Jitter Tolerance

36

Figure 21. Jitter Tolerance Mask/Template

36

Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)

37

Clock Multiplication (Si5316, Si5322, Si5323, Si5365, Si5366)

37

Clock Multiplication (Si5316)

37

Figure 22. Si5316 Divisor Ratios

38

Clock Multiplication (Si5322, Si5323, Si5365, Si5366)

39

CKOUT3 and CKOUT4 (Si5365 and Si5366)

51

Loop Bandwidth (Si5316, Si5322, Si5323, Si5365, Si5366)

51

Jitter Tolerance (Si5316, Si5323, Si5366)

51

Narrowband Performance (Si5316, Si5323, Si5366)

51

Input-To-Output Skew (Si5316, Si5323, Si5366)

51

Wideband Performance (Si5322 and Si5365)

51

Lock Detect (Si5322 and Si5365)

51

Input-To-Output Skew (Si5322 and Si5365)

51

PLL Self-Calibration

52

Input Clock Stability During Internal Self-Calibration (Si5316, Si5322, Si5323, Si5365, Si5366)

52

Self-Calibration Caused by Changes in Input Frequency (Si5316, Si5322, Si5323, Si5365, Si5366)

52

Pin Control Input Clock Control

54

Manual Clock Selection

54

Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366)

55

Hitless Switching with Phase Build-Out (Si5323, Si5366)

56

Digital Hold/Vco Freeze

57

Narrowband Digital Hold (Si5316, Si5323, Si5366)

57

Recovery from Digital Hold (Si5316, Si5323, Si5366)

57

Wideband VCO Freeze (Si5322, Si5365)

57

Frame Synchronization (Si5366)

57

Output Phase Adjust (Si5323, Si5366)

58

FSYNC Realignment (Si5366)

58

Including FSYNC Inputs in Clock Selection (Si5366)

58

FS_OUT Polarity and Pulse Width Control (Si5366)

58

Using FS_OUT as a Fifth Output Clock (Si5366)

58

Disabling FS_OUT (Si5366)

59

Output Clock Drivers

59

LVPECL and CMOS TQFP Output Signal Format Restrictions at 3.3 V (Si5365, Si5366)

59

PLL Bypass Mode

60

Alarms

60

Loss-Of-Signal Alarms (Si5316, Si5322, Si5323, Si5365, Si5366)

60

FOS Alarms (Si5365 and Si5366)

60

FSYNC Align Alarm (Si5366 and CK_CONF = 1 and FRQTBL = L)

61

C1B and C2B Alarm Outputs (Si5316, Si5322, Si5323)

61

C1B, C2B, C3B, and ALRMOUT Outputs (Si5365, Si5366)

61

Device Reset

62

Dspllsim Configuration Software

62

Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, and Si5376)

63

Clock Multiplication

63

Jitter Tolerance (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)

63

Wideband Parts (Si5325, Si5367)

63

Figure 23. Wideband PLL Divider Settings (Si5325, Si5367)

63

Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)

63

Narrowband Parts (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)

64

Figure 24. Narrowband PLL Divider Settings

65

Loop Bandwidth (Si5319, Si5326, Si5368, Si5375, and Si5376)

66

Lock Detect (Si5319, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)

66

PLL Self-Calibration

66

Initiating Internal Self-Calibration

67

Input Clock Stability During Internal Self-Calibration

67

Self-Calibration Caused by Changes in Input Frequency

67

Narrowband Input-To-Output Skew (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)

67

Clock Output Behavior before and During ICAL (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)

68

Input Clock Configurations (Si5367 and Si5368)

69

Input Clock Control

69

Figure 25. Si5324, Si5325, Si5326, Si5327, Si5328, Si5374

69

Manual Clock Selection (Si5324, Si5325, Si5326, Si5328, Si5367, Si5368, Si5369, Si5374, and Si5376)

70

Figure 26. Si5367, Si5368, and Si5369 Input Clock Selection

70

Automatic Clock Selection (Si5324, Si5325, Si5326, Si5328, Si5367, Si5368, Si5369, Si5374, and Si5376)

71

Hitless Switching with Phase Build-Out (Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, and Si5376)

72

Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376 Free Run Mode

73

Free Run Mode Programming Procedure

73

Clock Control Logic in Free Run Mode

73

Figure 27. Free Run Mode Block Diagram

73

Free Run Reference Frequency Constraints

74

Digital Hold

75

Narrowband Digital Hold (Si5316, Si5324, Si5326, Si5328, Si5368, Si5369, Si5374, Si5376)

75

Figure 28. Parameters in History Value of M

75

History Settings for Low Bandwidth Devices (Si5324, Si5327, Si5328, Si5369, Si5374)

77

Recovery from Digital Hold (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, and Si5376)

77

VCO Freeze (Si5319, Si5325, Si5367, Si5375)

77

Digital Hold Versus VCO Freeze

77

Figure 29. Digital Hold Vs. VCO Freeze Example

77

Output Phase Adjust (Si5326, Si5368)

78

Coarse Skew Control (Si5326, Si5368)

78

Fine Skew Control (Si5326, Si5368)

78

Independent Skew (Si5324, Si5326, Si5328, Si5368, Si5369, Si5374, and Si5376)

79

Output-To-Output Skew (Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, and Si5376)

79

Input-To-Output Skew (All Devices)

79

Frame Synchronization Realignment (Si5368 and CK_CONFIG_REG = 1)

79

Figure 30. Frame Sync Frequencies

80

FSYNC Realignment (Si5368)

81

FSYNC Skew Control (Si5368)

82

Including FSYNC Inputs in Clock Selection (Si5368)

82

FS_OUT Polarity and Pulse Width Control (Si5368)

82

Using FS_OUT as a Fifth Output Clock (Si5368)

82

Output Clock Drivers (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, Si5376)

83

Disabling Ckoutn

83

LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si5367, Si5368, Si5369)

83

PLL Bypass Mode (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, and Si5376)

84

Alarms (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, and Si5376)

84

Loss-Of-Signal Alarms (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, and Si5376)

84

FOS Algorithm (Si5324, Si5325, Si5326, Si5328, Si5368, Si5369, Si5374, and Si5376)

85

Figure 31. FOS Compare

86

C1B, C2B (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5374, Si5375, and Si5376)

87

LOS (Si5319, Si5375)

87

C1B, C2B, C3B, ALRMOUT (Si5367, Si5368, Si5369 [CK_CONFIG_REG = 0])

87

C1B, C2B, C3B, ALRMOUT (Si5368 [CK_CONFIG_REG = 1])

88

LOS Algorithm for Reference Clock Input (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)

89

LOL (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)

89

Device Interrupts

89

Device Reset

89

I 2 C Serial Microprocessor Interface

90

Figure 32. I 2 C Command Format

90

Figure 33. I2C Example

90

Serial Microprocessor Interface (SPI)

91

Figure 34. SPI Write/Set Address Command

92

Figure 35. SPI Read Command

92

Default Device Configuration

93

Register Descriptions

93

Dspllsim Configuration Software

93

Figure 36. SPI Timing Diagram

93

High-Speed I/O

94

Input Clock Buffers

94

Figure 37. Differential LVPECL Termination

94

Figure 38. Single-Ended LVPECL Termination

94

Figure 39. CML/LVDS Termination (1.8, 2.5, 3.3 V)

95

Figure 40. Center Tap Bypassed Termination

95

Figure 41. CMOS Termination (1.8, 2.5, 3.3 V)

95

Output Clock Drivers

96

LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si5367, Si5368, Si5369)

96

Typical Output Circuits

96

Figure 42. Typical Output Circuit (Differential)

96

Figure 43. Differential Output Example Requiring Attenuation

97

Figure 44. Typical CMOS Output Circuit (Tie Ckoutn+ and Ckoutn- Together)

97

Typical Clock Output Scope Shots

98

Figure 45. Differential CKOUT Structure (Not for CMOS)

98

Typical Scope Shots for SFOUT Options

99

Figure 47. Sfout_3, Lowswinglvds

99

Crystal/Reference Clock Interfaces (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5328, Si5366, Si5368, Si5369, Si5374, Si5375, and Si5376)

102

Figure 51. CMOS External Reference Circuit

102

Figure 52. Sinewave External Clock Circuit

102

Figure 53. Differential External Reference Input Example

103

(Not for Si5374, Si5375, or Si5376)

103

Figure 54. Differential OSC Reference Input Example for Si5374, Si5375 and Si5376

103

Three-Level (3L) Input Pins (no External Resistors)

104

Figure 55. Three Level Input Pins

104

Three-Level (3L) Input Pins (with External Resistors)

105

Figure 56. Three Level Input Pins

105

Power Supply

106

Figure 57. Typical Power Supply Bypass Network (TQFP Package)

106

Figure 58. Typical Power Supply Bypass Network (QFN Package)

106

Packages and Ordering Guide

107

Appendix A-Narrowband References

108

Figure 59. Typical Reference Jitter Transfer Function

109

Figure 60. Si5317 at 622.08 Mhz with a 40 Mhz Crystal

110

Figure 61. Si53Xx at 622.08 Mhz with a 114.285 Mhz Crystal

111

Appendix B-Frequency Plans and Typical Jitter Performance (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, Si5375, and Si5376)

112

Figure 62. Phase Noise for a Si5324 Using a 114.285 Mhz 3Rd OT Vs 114.285 Mhz Fundamental Crystal

112

Figure 63. 200 Mhz Output with a 40 Mhz Crystal Showing MID-Band Spurs

113

Figure 64. 200 Mhz Output with a 38.095 Mhz Crystal

114

Figure 65. Phase Noise Vs. F3

116

Figure 66. Jitter Integrated from 12 Khz to 20 Mhz Jitter, Fs RMS

117

Figure 67. Jitter Integrated from 100 Hz to 40 Mhz Jitter, Fs RMS

118

Appendix C-Typical Phase Noise Plots

119

Figure 68. Jitter Vs. F3 with FPGA

119

Figure 69. Reference Vs. Output Frequency

120

Figure 70. 622.08 Mhz Output with a 114.285 Mhz Crystal

121

Figure 71. 622.08 Mhz Output with a 40 Mhz Crystal

122

Figure 72. 155.52 Mhz In; 622.08 Mhz out

123

Figure 73. 155.52 Mhz In; 622.08 Mhz Out; Loop BW = 7 Hz, Si5324

124

Figure 74. 19.44 Mhz In; 156.25 Mhz Out; Loop BW = 80 Hz

125

Figure 75. 19.44 Mhz In; 156.25 Mhz Out; Loop BW = 5 Hz, Si5324

126

Figure 76. 27 Mhz In; 148.35 Mhz Out; Light Trace BW = 6 Hz; Dark Trace BW = 110 Hz

127

Figure 77. 61.44 Mhz In; 491.52 Mhz Out; Loop BW = 7 Hz, Si5324

128

Figure 78. 622.08 Mhz In; 672.16 Mhz Out; Loop BW = 6.9 Khz

129

Figure 79. 622.08 Mhz In; 672.16 Mhz Out; Loop BW = 100 Hz

130

Figure 80. 156.25 Mhz In; 155.52 Mhz out

131

Figure 81. 78.125 Mhz In; 644.531 Mhz out

132

Figure 82. 78.125 Mhz In; 690.569 Mhz out

133

Figure 83. 78.125 Mhz In; 693.493 Mhz out

134

Figure 84. 86.685 Mhz In; 173.371 Mhz and 693.493 Mhz out

135

Figure 85. 86.685 Mhz In; 173.371 Mhz out

136

Appendix D-Alarm Structure

137

Figure 86. 86.685 Mhz In; 693.493 Mhz out

137

Figure 87. 155.52 Mhz and 156.25 Mhz In; 622.08 Mhz out

138

Figure 88. 10 Mhz In; 1 Ghz out

139

Appendix E-Internal Pullup, Pulldown by Pin

140

Figure 89. Si5324, Si5326, and Si5328 Alarm Diagram

141

Figure 90. Si5368 and Si5369 Alarm Diagram (1 of 2)

142

Figure 91. Si5368 and Si5369 Alarm Diagram (2 of 2)

143

Appendix F-Typical Performance: Bypass Mode, PSRR

150

Crosstalk, Output Format Jitter

150

Appendix G-Near Integer Ratios

158

Figure 92. ±50 Ppm, 2 Ppm Steps

158

Figure 93. ±200 Ppm, 10 Ppm Steps

159

Figure 94. ±2000 Ppm, 50 Ppm Steps

159

Appendix H-Jitter Attenuation and Loop BW

160

Figure 95. RF Generator, Si5326, Si5324; no Jitter (for Reference)

161

Figure 96. RF Generator, Si5326, Si5324 (50 Hz Jitter)

161

Figure 97. RF Generator, Si5326, Si5324 (100 Hz Jitter)

162

Figure 98. RF Generator, Si5326, Si5324 (500 Hz Jitter)

162

Figure 99. RF Generator, Si5326, Si5324 (1 Khz Jitter)

163

Figure 100. RF Generator, Si5326, Si5324 (5 Khz Jitter)

163

Figure 101. RF Generator, Si5326, Si5324 (10 Khz Jitter)

164

Appendix I-Response to a Frequency Step Function

165

Figure 102. Si5326 Frequency Step Function Response

165

Appendix J-Si5374, Si5375, Si5376 PCB Layout Recommendations

166

Figure 103. VDD Plane

166

Figure 104. Ground Plane and Reset

167

Figure 105. Output Clock Routing

168

Appendix K-Si5374, Si5375, and Si5376 Crosstalk

170

Figure 107. Si5374, Si5375, and Si5376 DSPLL a

171

Figure 108. Si5374, Si5375, and Si5376 DSPLL B

172

Figure 109. Si5374, Si5375, and Si5376 DSPLL C

173

Figure 110. Si5374, Si5375, and Si5376 DSPLL D

174

Figure 111. Example Frequency Plan Sources

175

Figure 112. Run Time Frequency Plan Examples

176

Appendix L-Jitter Transfer and Peaking

177

Figure 113. Wide View of Jitter Transfer

177

Contact Information

178

Figure 114. Zoomed View of Jitter Transfer

178

Figure 115. Zoomed Again View of Jitter Transfer (Showing Peaking)

178

Figure 116. Maximum Zoomed View of Jitter Peaking

179

Document Change List

180

Silicon Laboratories SI5365 Generator Manuals

Silicon Laboratories SI5365 Reference Manual (184 pages)

Table of Contents

1 Any-Frequency Precision Clock Product Family Overview

2 Wideband Devices

3 Any-Frequency Clock Family Members

4 Device Specifications

5 DSPLL (All Devices)

6 Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)

7 Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)

8 High-Speed I/O

9 Power Supply

10 Packages and Ordering Guide

Appendix A-Narrowband References

Appendix B-Frequency Plans and Jitter Performance (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, Si5375)

Appendix C-Typical Phase Noise Plots

Appendix D-Alarm Structure

Appendix E-Internal Pullup, Pulldown by Pin

Appendix F-Typical Performance: Bypass Mode, PSRR, Crosstalk

Appendix G-Near Integer Ratios

Appendix H-Jitter Attenuation and Loop BW

Appendix I-Si5374 and Si5375 PCB Layout Recommendations

Appendix J-Si5374 and Si5375 Crosstalk

Appendix K-Jitter Transfer and Peaking

Document Change List

Contact Information

Silicon Laboratories SI5365 Family Reference Manual (182 pages)

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