I2C Interface; Slave Address - Silicon Laboratories SI5351A/B/C Product Manual

I2c-programmable any-frequency cmos clock generator + vcxo
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Si5351A/B/C
2
4. I
C Interface
Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the
2
I
C interface. The following is a list of the common features that are controllable through the I
summary of register functions is shown in Section 7.
Read Status Indicators
Loss of signal (LOS) for the CLKIN input

Loss of lock (LOL) for PLLA and PLLB

Configuration of multiplication and divider values for the PLLs, MultiSynth dividers
Configuration of the Spread Spectrum profile (down or center spread, modulation percentage)
Control of the cross point switch selection for each of the PLLs and MultiSynth dividers
Set output clock options
Enable/disable for each clock output

Invert/non-invert for each clock output

Output divider values (2

Output state when disabled (stop hi, stop low, Hi-Z)

Output phase offset

2
The I
C interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or
Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.
2
The I
C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 7.
Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the
2
I
C specification.
The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed address plus a user selectable LSB bit as
shown in Figure 8. The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful for applications that
require more than one Si5351 on a single I
Data is transferred MSB first in 8-bit words as specified by the I
bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 9. A write
burst operation is also shown where every additional data word is written using to an auto-incremented address.
14
n
, n=1.. 7)
VDD
>1k
>1k
SCL
2
I
C Bus
SDA
4.7 k
INTR
2
I
C Address Select:
A0
Pull-up to VDD (A0 = 1)
Pull-down to GND (A0 = 0)
2
Figure 7. I
C and Control Signals
2
C bus.
6

Slave Address

1
Figure 8. Si5351 I
Preliminary Rev. 0.95
Si5351
5
4
3
2
1
0
1
0
0
0
0 0/1
A0
2
C Slave Address
2
C specification. A write command consists of a 7-
2
C interface. A

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