Silicon Laboratories Si5342 Family Reference Manual
  1. Manuals
  2. Brands
  3. Silicon Laboratories Manuals
  4. Computer Hardware
  5. Si5342
  6. Family reference manual

Silicon Laboratories Si5342 Family Reference Manual

Any-frequency, any-output jitter-attenuators /clock multipliers rev. d
Hide thumbs
Table of Contents

Advertisement

Quick Links

A
- F
, A
- O
NY
REQUENCY
NY
UTPUT
J
- A
/ C
M
I T T E R
TTENUATORS
LOCK
ULTIPLIERS
S i 5 345 , S i 534 4 , S i5 3 4 2 R
. D
EV
F
R
M
AMILY
EFERENCE
ANUAL
Rev. 1.0 7/16
Copyright © 2016 by Silicon Laboratories
Si5345-44-42-D-RM

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Si5342 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Silicon Laboratories Si5342

Summary of Contents for Silicon Laboratories Si5342

  • Page 1 REQUENCY UTPUT I T T E R TTENUATORS LOCK ULTIPLIERS S i 5 345 , S i 534 4 , S i5 3 4 2 R AMILY EFERENCE ANUAL Rev. 1.0 7/16 Copyright © 2016 by Silicon Laboratories Si5345-44-42-D-RM...

  • Page 2: Table Of Contents

    Si5345-44-42-D-RM ABLE O F ONTENTS Section Page 1. Scope ..............9 1.1.
  • Page 3 12.2.1. Si5342/44 Applications without a Crystal........
  • Page 4 14.5. Si5342 Register Definitions ........
  • Page 5 Figure 1. Block Diagram Si5345/44/42 ......... . 10 Figure 2. Si5342 DSPLL and Multisynth System Flow Diagram ..... . . 11 Figure 3.
  • Page 6 Si5345-44-42-D-RM Figure 42. Crystal Ground Plane (Layer 3) ........70 Figure 43.
  • Page 7 Si5345-44-42-D-RM I S T OF ABLES Table Page Table 1. Product Selection Guide ..........9 Table 2.
  • Page 8 Si5345-44-42-D-RM Table 42. Pre-Scale Divide Ratio Register ........67 Table 43.

  • Page 9: Scope

    2.2. Family Product Comparison Table 1 lists a comparison of the different family members. Table 1. Product Selection Guide Part Number Number of Inputs Number of MultiSynths Number of Outputs Package Type Si5342 44-QFN Si5344 44-QFN Si5345 64-QFN Rev. 1.0...

  • Page 10: Available Software Tools And Support

    Si5345-44-42-D-RM Si5345/44/42 48-54MHz XTAL or REFCLK IN_SEL[1:0] ÷ PXAXB ÷ DSPLL ÷ ÷ IN3/FB_IN ÷ ÷ IN3/FB_IN Optional External Feedback VDDO0 Multi ÷ OUT0 ÷R Synth OUT0 Multi VDDO1 ÷ OUT1 ÷R Synth OUT1 Multi VDDO2 ÷ OUT2 Synth ÷R OUT2 Multi VDDO3...

  • Page 11: Dspll And Multisynth

    OUT1 Synth OUT1 Figure 2. Si5342 DSPLL and Multisynth System Flow Diagram The frequency configuration of the DSPLL is programmable through the SPI or I C serial interface and can also be stored in non-volatile memory or RAM. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), fractional output MultiSynth division (Nn/Nd), and integer output division (Rn) allows the generation of virtually any output frequency on any of the outputs.

  • Page 12: Dividers

    Si5345-44-42-D-RM 3.1. Dividers There are five divider classes within the Si5345/4/2. See Figure 1 for a block diagram that shows all of these dividers. Wide range input dividers P3, P2, P1, P0  MultiSynth divider  48 bit numerator, 32 bit denominator ...

  • Page 13: Fastlock Feature

    Si5345-44-42-D-RM 3.2.1. Fastlock Feature Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The Fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process to reduce lock time. Higher Fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock Bandwidth settings in the range from 100 Hz up to 4 kHz are available for selection.

  • Page 14: Modes Of Operation

    Si5345-44-42-D-RM 4. Modes of Operation After initialization the DSPLL will operate in one of the following modes: Free-run, lock-acquisition, locked, or holdover. See Figure 3 below for the state diagram showing the modes of operation. The following sections describe each of these modes in greater detail. Power-Up Reset and Initialization...

  • Page 15: Figure 4. Si5345/44/42 Memory Configuration

    Si5345-44-42-D-RM Figure 4. Si5345/44/42 Memory Configuration Table 5. Reset Registers Register Name Function Address [Bit Field] HARD_RST 0x001E[1] Performs the same function as power cycling the device. All registers will be restored to their default values. SOFT_RST 0x001C[0] Performs a soft reset. Initiates register configuration changes. Hard Reset Power-Up bit asserted...

  • Page 16: Dynamic Pll Changes

    Si5345-44-42-D-RM 4.2. Dynamic PLL Changes 4.2.1. Revision B and A It is possible for a PLL to become unresponsive (i.e., lose lock indefinitely) when it is dynamically reprogrammed or changed via the serial port. Reprogramming/changing the N divider does not affect the PLL. Any change that causes the VCO frequency to change by more than 250 ppm since Power-up, NVM download, or SOFT_RST requires the following special sequence of writes.

  • Page 17: Nvm Programming

    Si5345-44-42-D-RM 4.3. NVM Programming The NVM is two time writable. Because it can only be written two times, it is important to configure the registers correctly before beginning the NVM programming process. Once a new configuration has been written to NVM, the old configuration is no longer accessible.

  • Page 18: Holdover Mode

    Si5345-44-42-D-RM 4.7. Holdover Mode The DSPLL will automatically enter Holdover mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. It uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit stores up to 120 seconds of historical frequency data while locked to a valid clock input.

  • Page 19: Table 7. Holdover Mode Control Registers

    Si5345-44-42-D-RM Table 7. Holdover Mode Control Registers Register Name Function Address [Bit Field] Holdover Status HOLD 0x000E[5] DSPLL Holdover status indicator. 0: Normal Operation 1: In Holdover/Freerun Mode: HOLD_HIST_VALID = 0 ≥ Freerun Mode HOLD_HIST_VALID = 1 ≥ Holdover Mode HOLD_FLG 0x0013[5] Holdover indicator sticky flag bit.
  • Page 20 Si5345-44-42-D-RM Table 7. Holdover Mode Control Registers (Continued) Register Name Function Address [Bit Field] Holdover Exit Control HOLD_RAMP_BYP 0x052C[3] Holdover Exit Ramp Bypass 0: Use Ramp when exiting from Holdover (default) 1: Use Holdover/Fastlock/Loop bandwidth when exiting from Holdover HOLDEXIT_BW_SEL0 0x059B[6] Select the exit bandwidth from Holdover when ramped exit is not selected (HOLD_RAMP_BYP = 1).

  • Page 21: Clock Inputs

    Si5345-44-42-D-RM 5. Clock Inputs The Si5342/44/45 support 4 inputs that can be used to synchronize to the internal DSPLL. 5.1. Inputs (IN0, IN1, IN2, IN3) The inputs accept both standard format inputs and low-duty-cycle pulsed CMOS clocks. Input selection from CLK_SWITCH_MODE can be manual (pin or register controlled) or automatic with user definable priorities.

  • Page 22: Automatic Input Selection

    Si5345-44-42-D-RM 5.1.2. Automatic Input Selection In automatic mode CLK_SWITCH_MODE = 0x01 (non-revertive) or 0x02 (revertive) An automatic input selection is available in addition to the above mentioned manual switching option described in “5.1.1. Manual Input Switching”. In automatic mode, the selection criteria is based on input clock qualification, input priority and the revertive option.

  • Page 23: Types Of Inputs

    Si5345-44-42-D-RM 5.2. Types of Inputs Each of the four different inputs IN0-IN3 can be configured as standard LVDS, LVPECL, HCL, CML, and single- ended LVCMOS formats, or as a low duty cycle pulsed CMOS format. The standard format inputs have a nominal 50% duty cycle, must be AC-coupled and use the “Standard”...

  • Page 24: Unused Inputs

    Si5345-44-42-D-RM Input clock buffers are enabled by setting the IN_EN 0x0949[3:0] bits appropriately for IN3 through IN0. Unused clock inputs may be powered down and left unconnected at the system level. For standard mode inputs, both input pins must be properly connected as shown in Figure 7 above, including the “Standard AC Coupled Single Ended” case.

  • Page 25: Ramped Input Switching

    Si5345-44-42-D-RM 5.2.3. Ramped Input Switching If switching between input clocks that are not exactly the same frequency (i.e. are plesiochronous), ramped switching should be enabled to ensure a smooth transition between the two inputs. In this situation, it is also advisable to enable phase buildout to minimize the input-to-output clock skew after the clock switch ramp has completed.

  • Page 26: Synchronizing To Gapped Input Clocks

    Figure 9 shows the fault monitors for each input path going into the DSPLL, which includes the crystal input as well as IN0-3. Si5345/44/42 Precision ÷P Fast DSPLL Precision ÷P Fast Precision ÷P Fast ÷M IN3/FB_IN Precision ÷P Fast IN3/FB_IN Figure 9. Si5342/44/45 Fault Monitors Rev. 1.0...

  • Page 27: Input Loss Of Signal (Los) Fault Detection

    Si5345-44-42-D-RM 5.3.1. Input Loss of Signal (LOS) Fault Detection The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors.

  • Page 28: Out Of Frequency (Oof) Fault Detection

    Si5345-44-42-D-RM Table 14. Loss of Signal Status Monitoring and Control Registers (Continued) Register Name Function Address [Bit Field] LOS_TRIG_THR 0x002E[7:0]- Sets the LOS trigger threshold and clear sensitivity for IN3, IN2, IN1, IN0. 0x0035[7:0] These 16- bit values are determined by ClockBuilder Pro LOS_CLR_THR 0x0036[7:0]- 0x003D[7:0]...

  • Page 29: Loss Of Lock Fault Monitoring

    Si5345-44-42-D-RM Table 15 lists the OOF monitoring and control registers. Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency.

  • Page 30: Figure 13. Lol Status Indicators

    Si5345-44-42-D-RM 4. Clear delay a. CBPro sets this based upon the project plan A block diagram of the LOL monitor is shown in Figure 13. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects the current state of the LOL monitor.
  • Page 31 Si5345-44-42-D-RM Table 16. Loss of Lock Status Monitor and Control Registers LOL_TIMER_EN 0x00A2[1] Allows bypassing the LOL clear delay timer. 0-bypassed, 1-enabled. Set by CBPro. Sets 417 s as time without an input to assert LOL. Set by LOL_NOSIG_TIME 0x02B7[3:2] CBPro.

  • Page 32: Interrupt Configuration

    Si5345-44-42-D-RM 5.4. Interrupt Configuration There is an interrupt pin available on the device which is used to indicate a change in state of one or several of the status indicators. Any of the status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTR pin is reset by clearing the status register that caused the interrupt.

  • Page 33: Output Clocks

    Si5345-44-42-D-RM 6. Output Clocks Each driver has a configurable voltage swing and common mode voltage covering a wide variety of differential signal formats including LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3, 2.5, or 1.8 V) providing up to 20 single-ended outputs or any combination of differential and single-ended outputs.

  • Page 34: Table 17. Output Driver Crosspoint Configuration Registers

    Table 17 is used to set up the routing from the MultiSynth frequency selection to the output. Table 17. Output Driver Crosspoint Configuration Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_MUX_SEL 0x010B[2:0] 0x0115[2:0] 0x0115[2:0] Connects the output drivers to one of the N dividers. Selections are N0, N1, N2, N3, N4...

  • Page 35: Performance Guidelines For Outputs

    Whenever a number of high frequency, fast rise time, large amplitude signals are all close to one another, the laws of physics dictate that there will be some amount of crosstalk. The jitter of the Si5342/44/45 is so low that crosstalk can become a significant portion of the final measured output jitter.

  • Page 36: Output Signal Format

    See “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for additional information. Table 19. Output Signal Format Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_FORMAT 0x0109[2:0] 0x0113[2:0] 0x0113[2:0] Selects the output signal format as dif- OUT1_ FORMAT...

  • Page 37: Differential Output Terminations

    Si5345-44-42-D-RM 6.3.1. Differential Output Terminations The differential output drivers support both ac and dc-coupled terminations as shown in Figure 17. AC Coupled LVDS/LVPECL DC Coupled LVDS = 3.3 V, 2.5 V, 1.8 V = 3.3 V, 2.5 V OUTx OUTx OUTx OUTx Internally...

  • Page 38: Programmable Common Mode Voltage For Differential Outputs

    Si5345-44-42-D-RM Table 20. Differential Output Voltage Swing Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_AMPL 0x010A[6:4] 0x0114[6:4] 0x0114[6:4] Sets the voltage swing for the differ- OUT1_ AMPL 0x010F[6:4] 0x0119[6:4] 0x0119[6:4] ential output drivers for both normal and...

  • Page 39: Lvcmos Output Terminations

    Si5345-44-42-D-RM 6.3.4. LVCMOS Output Terminations LVCMOS outputs are dc-coupled as shown in Figure 19. DC Coupled LVCMOS 3.3V, 2.5V, 1.8V LVCMOS = 3.3V, 2.5V, 1.8V OUTx OUTx Figure 19. LVCMOS Output Terminations 6.3.5. LVCMOS Output Impedance and Drive Strength Selection Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths.

  • Page 40: Lvcmos Output Signal Swing

    Si5345-44-42-D-RM Table 23. LVCMOS Drive Strength Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_CMOS_DRV 0x0109[7:6] 0x0113[7:6] 0x0113[7:6] LVCMOS output impedance. OUT1_ CMOS_DRV 0x010E[7:6] 0x0118[7:6] 0x0118[7:6] OUT2_ CMOS_DRV 0x0113[7:6] 0x0127[7:6] — OUT3_ CMOS_DRV 0x0118[7:6] 0x012C[7:6] —...

  • Page 41: Lvcmos Output Polarity

    The polarity of these clocks is configurable enabling complimentary clock generation and/or inverted polarity with respect to other output drivers. Table 24. LVCMOS Output Polarity Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_INV 0x010B[7:6] 0x0115[7:6] 0x0115 [7:6] Controls the output polarity of the OUTx OUT1_ INV...

  • Page 42: Output Driver Settings For Lvpecl, Lvds, Hcsl, And Cml

    Si5345-44-42-D-RM 6.3.8. Output Driver Settings for LVPECL, LVDS, HCSL, and CML Each differential output has four settings for control 1. Normal or Low Power Format 2. Amplitude (sometimes called Swing) 3. Common Mode Voltage 4. Stop High or Stop Low The normal Format setting has a 100 ohm internal resistor between the plus and minus output pins.

  • Page 43: Output Enable/Disable

    Table 27. Output Enable/Disable Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUTALL_ 0x0102[0] 0x0102[0] 0x0102[0] Disables all output drivers: 0 - all out- DISABLE_LOW puts disabled, 1 – all outputs enabled.

  • Page 44: Output Driver State When Disabled

    The disabled state of an output driver is configurable as disable low or disable high. Table 28. Output Driver State Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_DIS_STATE 0x0109[5:4] 0x0113[5:4] 0x0113[5:4] Determines the state of an output driver when...

  • Page 45: Output Skew Control (T0-T4)

    Si5345-44-42-D-RM 6.5. Output Skew Control (t0–t4) The Si5345 uses independent MultiSynth dividers (N0 - N4) to generate up to 5 unique frequencies to its 10 outputs through a crosspoint switch. By default all clocks are phase aligned. A delay path (t0–t4) associated with each of these dividers is available for applications that need a specific output skew configuration.

  • Page 46: Output Buffer Supply Voltage Selection

    RST pin. Table 30. Output Delay Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 N0_DELAY 0x0359[7:0]- 0x0359[7:0]- 0x0359[7:0]- Configures path delay values for each N 0x035A[7:0] 0x035A[7:0] 0x035A[7:0] divider.

  • Page 47: Zero Delay Mode

    Si5345. OUT3 and FB_IN pins are recommended for the external feedback in the Si5344. OUT1 or OUT2 are recommended with FB_IN in the Si5342. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is necessary for best performance.

  • Page 48: Table 32. Zero Delay Mode Registers

    Si5345-44-42-D-RM Table 32. Zero Delay Mode Registers Register Name Hex Address Function [Bit Field] ZDM_EN 0x0487[0] 0: Disable zero delay mode. 1: Enable zero delay mode. ZDM_IN_SEL 0x0487[2:1] Selects (normal feedback IN0-IN3) by creating an external feedback through FB_IN (zero delay mode). ZDM_AUTOSW_EN 0x0487[4] 0: Automatic switching disabled for zero-delay mode...

  • Page 49: Digitally-Controlled Oscillator (Dco) Mode

    Si5345-44-42-D-RM 8. Digitally-Controlled Oscillator (DCO) Mode An output that is controlled as a DCO is useful for simple tasks, such as frequency margining, CPU speed control, or just changing the output frequency. The output can also be used for more sophisticated tasks, such as FIFO management, by adjusting the frequency of the read or write clock to the FIFO or using the output as a variable Local Oscillator in a radio application.

  • Page 50: Figure 22. Dco With Finc/Fdec Pins Or Bits

    Si5345-44-42-D-RM Si5345 N0_FSTEP_MASK Multi ÷ 0x0339 Synth Frequency Step Word 0x033B – 0x0340 N1_FSTEP_MASK Multi ÷ 0x0339 Synth Frequency Step Word 0x0341 – 0x0346 N2_FSTEP_MASK Multi ÷ 0x0339 Synth FINC Frequency FDEC Step Word 0x001D 0x0347 – 0x034C N3_FSTEP_MASK Multi ÷...

  • Page 51: Dco With Direct Register Writes

    Si5345-44-42-D-RM Table 34. Frequency Increment/Decrement Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 FINC 0x001D[0] 0x001D[0] 0x001D[0] Asserting this bit will increase the DSPLL output frequency by the frequency step word. FDEC 0x001D[1] 0x001D[1] 0x001D[1] Asserting this bit will decrease the DSPLL output frequency by the frequency step word.

  • Page 52: Serial Interface

    Si5345-44-42-D-RM 9. Serial interface Configuration and operation of the Si5345/44/42 is controlled by reading and writing registers using the I C or SPI interface. Both of these serial interfaces are based on 8-bit addressing, which means that the page byte must be written every time you need to access a different page in the register map.

  • Page 53: I2C Interface

    Si5345-44-42-D-RM 9.1. I C Interface When in I C mode, the serial interface operates in slave mode with 7-bit addressing and can operate in Standard- Mode (100 kbps) or Fast-Mode (400 kbps) and supports burst data transfer with auto address increments. The I bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 26.

  • Page 54: Figure 26. I2C Write Operation

    Si5345-44-42-D-RM Write Operation – Single Byte Slv Addr [6:0] A Reg Addr [7:0] Data [7:0] Write Operation - Burst (Auto Address Increment) Slv Addr [6:0] A Reg Addr [7:0] Data [7:0] Data [7:0] Reg Addr +1 1 – Read Host Si5345/44/42 0 –...

  • Page 55: Spi Interface

    Si5345-44-42-D-RM Table 36. SMBus Timeout Error Bit Indicators Register Name Function Address [Bit Field] 0x000C[5] 1 if there is a SMBus timeout error. Contact Silicon Labs. SMBUS_TIMEOUT 0x0011[5] 1 if there is a SMBus timeout error. Contact Silicon Labs. SMBUS_TIMEOUT_FLG 9.2.

  • Page 56: Figure 29. Example Writing Three Data Bytes Using The Write Commands

    Si5345-44-42-D-RM Writing or reading data consist of sending a “Set Address” command followed by a “Write Data” or “Read Data” command. The 'Write Data + Address Increment' or “Read Data + Address Increment” commands are available for cases where multiple byte operations in sequential address locations is necessary. The “Burst Write Data” instruction provides a compact command format for writing data since it uses a single instruction to define starting address and subsequent data bytes.

  • Page 57: Figure 30. Example Of Reading Three Data Bytes Using The Read Commands

    Si5345-44-42-D-RM ‘Set Address’ and ‘Read Data’ ‘Set Addr’ Addr [7:0] ‘Read Data’ Data [7:0] ‘Set Addr’ Addr [7:0] ‘Read Data’ Data [7:0] ‘Set Addr’ Addr [7:0] ‘Read Data’ Data [7:0] ‘Set Address’ and ‘Read Data + Address Increment’ ‘Set Addr’ Addr [7:0] ‘Read Data + Addr Inc’...

  • Page 58: Figure 32. Spi "Write Data" And "Write Data+ Address Increment" Instruction Timing

    Si5345-44-42-D-RM Previous ‘Write Data’ or ‘Write Data + Address Increment’ Next Command Command Command > 2.0 > 2 SCLK SCLK Periods Periods Write Data instruction Data byte @ base address + 1 SCLK 4-Wire 3-Wire SDIO Host Si5345/44/42 Don’t Care High Impedance Host Si5345/44/42...

  • Page 59: Figure 33. Spi "Read Data" And "Read Data + Address Increment" Instruction Timing

    Si5345-44-42-D-RM Previous ‘Read Data’ or ‘Read Data + Address Increment’ Next Command Command Command > 2.0 > 2.0 SCLK SCLK Periods Periods Read Data instruction Read byte @ base address + 1 SCLK 4-Wire 3-Wire SDIO Host Si5345/44/42 Don’t Care High Impedance Host Si5345/44/42...

  • Page 60: Field Programming

    Si5345-44-42-D-RM 10. Field Programming To simplify design and software development of systems using the Si5345/44/42, a field programmer is available. The ClockBuilder Pro Field Programmer supports both “in-system” programming (for devices already mounted on a PCB), as well as “in-socket” programming of Si5345/44/42 sample devices. Refer to www.silabs.com/ CBProgrammer for information about this kit.

  • Page 61: Xaxb External References

    Si5345-44-42-D-RM 11. XAXB External References 11.1. Performance of External References An external standard non-pullable crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter reference clock for the DSPLL and for providing a stable reference for the free-run and holdover modes.

  • Page 62: Figure 36. Clipped Sine Wave Tcxo Output

    Si5345-44-42-D-RM V3P3 Si5345/44/42 100 nF TCXO 100 nF Figure 36. Clipped Sine Wave TCXO Output V3P3 Si5345/44/42 TCXO  100 nF  100 nF 100 nF Figure 37. CMOS TCXO Output The Si5345/44/42 can also accommodate an external reference clock (REFCLK) instead of a crystal. Selection between the external XTAL or REFCLK is controlled by XAXB_EXTCLK_EN, the LSB of register 0x090E.

  • Page 63: Recommended Crystals

    11.2. Recommended Crystals There are two classes of crystals that are recommended: those that are tested over temperature for activity dips and those that are not. There is a cost premium for testing over temperature. An activity dip is defined as when the crystal oscillation frequency deviates by more than 2 ppm from its expected frequency vs.
  • Page 64 Table 38. Recommended Crystals (Continued) Supplier Part Number Frequency Initial Accuracy over Tested Drive Case Size Tolerance –40 °C to +85 °C Max pF Max W over Level µW mm x mm in ± ppm in ± ppm Temp Activity Dips? Kyocera CX3225SB48000D0FPJC2...

  • Page 65: Figure 38. Maximum Esr Vs. C0 For 25 Mhz Crystal

    Si5345-44-42-D-RM Maximum ESR vs C0 for 25 MHz Crystal C0 pf Figure 38. Maximum ESR vs. C0 for 25 MHz Crystal Maximum ESR vs C0 for 48 54 MHz Crystal C0 pf Figure 39. Maximum ESR vs. C0 for 48–54 MHz Crystal Rev.

  • Page 66: Recommended Oscillators

    Si5345-44-42-D-RM 11.3. Recommended Oscillators Table 39 lists recommended TCXO suppliers. Table 39. Recommended Oscillator Suppliers Supplier Part Number TCXO/ Frequency Case OCXO Size (mm x mm x mm) Epson TG-5500CA-68N- TCXO 49.152 MHz 49.1520000MHz Epson TG-5500-67N-40.00000MHz TCXO 40 MHz Rakon 513872 (40MHz RTX7050A TCXO 40.000...

  • Page 67: Pxaxb Pre-Scale Divide Ratio For Reference Clock Register

    Si5345-44-42-D-RM 11.4.3. PXAXB Pre-scale Divide Ratio for Reference Clock Register Table 42. Pre-Scale Divide Ratio Register Register Name Function Address [Bit Field] PXAXB 0206[1:0] This is a two bit value that sets the divider value. Table 43 lists the input values for the two-bit field and the corresponding divider values. Table 43.

  • Page 68: Crystal And Device Circuit Layout Recommendations

    4. Control and Status signals to input or output clock trace coupling 5. Xtal signal coupling 6. Xtal layout (See “12.1.2. Si5345 Crystal Guidelines” and “12.2.2. Si5342/44 Crystal Guidelines” for important crystal layout guidelines.) If the application uses a crystal for the XAXB inputs a shield should be placed underneath the crystal connected to the X1 and X2 pins (4 and 7) to provide the best possible performance.

  • Page 69: Figure 40. 64-Pin Si5345 Crystal Layout Recommendations Top Layer (Layer 1)

    Si5345-44-42-D-RM 5. In general do not route GND, power planes/traces, or locate components on the other side, below the crystal GND shield. As an exception if it is absolutely necessary to use the area on the other side of the board for layout or routing, then place the next reference plane in the stack-up at least two layers away or at least 0.05 inches away.

  • Page 70: Figure 42. Crystal Ground Plane (Layer 3)

    Si5345-44-42-D-RM Figure 42 is the ground plane and shows a void underneath the crystal shield. Figure 43 is a power plane and shows the clock output power supply traces. The void underneath the crystal shield is continued. Figure 42. Crystal Ground Plane (Layer 3) Figure 43.

  • Page 71: Figure 44. Layer 5 Power Routing On Power Plane (Layer 5)

    Si5345-44-42-D-RM Figure 44 shows layer 5, which is the power plane with the power routed to the clock output power pins. Figure 44. Layer 5 Power Routing on Power Plane (Layer 5) Figure 45 is another ground plane similar to layer 3. Figure 45.

  • Page 72: Output Clocks

    Si5345-44-42-D-RM 12.1.3. Output Clocks Figure 46 shows the output clocks. Similar to the input clocks the output clocks have vias that immediately go to a buried layer with a ground plane above them and a ground flooded bottom layer. There is a ground flooding between the clock output pairs to avoid crosstalk.

  • Page 73: 44-Pin Qfn Si5344/42 Layout Recommendations

    Si5345-44-42-D-RM 12.2. 44-Pin QFN Si5344/42 Layout Recommendations This section details the layout recommendations for the 44-pin Si5344 and Si5342 devices using an example 6- layer PCB. The following guidelines details images of a six layer board with the following stack: Layer 1: device layer, with low speed CMOS control/status signals, ground flooded ...

  • Page 74: Si5342/44 Crystal Guidelines

    Si5345-44-42-D-RM 12.2.2. Si5342/44 Crystal Guidelines Figure 49 is the second layer. The second layer implements the shield underneath the crystal. The shield extends underneath the entire crystal and the X1 and X2 pins. There should be no less than 12 vias to connect the X1 and X2 planes on layers 1 and 2.

  • Page 75: Figure 51. Power Plane And Clock Output Power Supply Traces (Layer 4)

    Si5345-44-42-D-RM Figure 51 is a power plane showing the clock output power supply traces. The void underneath the crystal shield is continued. Figure 51. Power Plane and Clock Output Power Supply Traces (Layer 4) Figure 52 shows layer 5 and the clock input traces. Similar to the clock output traces, they are routed to an inner layer and surrounded by ground to avoid crosstalk.

  • Page 76: Figure 53. Low-Speed Cmos Control And Status Signal Layer 6 (Bottom Layer)

    Si5345-44-42-D-RM Figure 53 shows the bottom layer, which continues the void underneath the shield. Layer 6 and layer 1 are mainly used for low speed CMOS control and status signals for which crosstalk is not a significant issue. PCB ground can be placed under the XTAL Ground shield (X1/X2) as long as the PCB ground is at least 0.05 inches below it.

  • Page 77: Power Management

    Table 44. Power-Down Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 0x001E[0] 0x001E[0] 0x001E[0] This bit allows the device to be powered down. The serial interface remains pow- ered. OUT0_PDN...

  • Page 78: Power Supply Recommendations

    Si5345-44-42-D-RM 13.2. Power Supply Recommendations The power supply filtering generally is important for optimal timing performance. The Si5345/44/42 devices have multiple stages of on-chip regulation to minimize the impact of board level noise on clock jitter. Following conventional power supply filtering and layout techniques will further minimize signal degradation from the power supply.

  • Page 79: Register Map

    Si5345-44-42-D-RM 14. Register Map 14.1. Base vs. Factory Preprogrammed Devices The Si5345/44/42 devices can be ordered as “base” or “factory-preprogrammed” (also known as “custom OPN”) versions. 14.1.1. “Base” Devices (a.k.a. “Blank” Devices) Example “base” orderable part numbers (OPNs) are of the form “Si5345A-A-GM” or “Si5344B-A-GM”. ...

  • Page 80: Register Map Overview And Default Settings Values

    Register map settings values are listed in the datasheet addendum, which can also be accessed by using the link above.The register maps are broken out for the Si5345, Si5344, and Si5342 separately. Table 45. Register Map Paging Descriptions Page...

  • Page 81: Si5345 Register Map

    Si5345-44-42-D-RM 14.3. Si5345 Register Map 14.3.1. Page 0 Registers Si5345 Register 0x0000 Die Rev Reg Address Bit Field Type Name Description 0x0000 DIE_REV 4- bit Die Revision Number Register 0x0001 Page Reg Address Bit Field Type Name Description 0x0001 PAGE Selects one of 256 possible pages.
  • Page 82 Si5345-44-42-D-RM Register 0x0005 Device Revision Reg Address Bit Field Type Name Description 0x0005 DEVICE_REV One ASCII character indicating the device revision level. 0 = A; 1 = B, etc. Example Si5345C-A12345-GM, the device revision is “A” and stored as 0 Register 0x0006–0x0008 TOOL_VERSION Reg Address Bit Field...
  • Page 83 Si5345-44-42-D-RM Si5345C-A-GM. Applies to a “base” or “non-custom” OPN device. Base devices are factory pre-programmed to a specific base part type (e.g., Si5345 but exclude any user-defined frequency plan or other user-defined operating characteristics selected in ClockBuilder Pro. Register 0x000B I C Address Setting Name Reg Address...
  • Page 84 Si5345-44-42-D-RM Register 0x000E Holdover and LOL Status Reg Address Bit Field Type Name Description 0x000E 1 if the DSPLL is out of lock 0x000E HOLD 1 if the DSPLL is in holdover (or free run) These status bits indicate if the DSPLL is in holdover and if it is in Loss of Lock. These bits are not sticky. Register 0x000F Calibration Status Reg Address Bit Field...
  • Page 85 Si5345-44-42-D-RM These are the sticky flag versions of register 0x000D. These bits are cleared by writing 0 to the bits that have been set. Input 0 (IN0) corresponds to LOS_FLG 0x0012 [0], OOF_FLG 0x0012 [4]  Input 1 (IN1) corresponds to LOS_FLG 0x0012 [1], OOF_FLG 0x0012 [5] ...
  • Page 86 Si5345-44-42-D-RM Register 0x0018 OOF and LOS Masks Reg Address Bit Field Type Name Description 0x0018 LOS_INTR_MSK 1 to mask the clock input LOS flag 0x0018 OOF_INTR_MSK 1 to mask the clock input OOF flag These are the interrupt mask bits for the OOF and LOS flags in register 0x0012. Input 0 (IN0) corresponds to LOS_INTR_MSK 0x0018 [0], OOF_INTR_MSK 0x0018 [4] ...

  • Page 87: Figure 54. Finc, Fdec Logic Diagram

    Si5345-44-42-D-RM Register 0x001D FINC, FDEC Reg Address Bit Field Type Name Description 0x001D FINC 1 a rising edge will cause the selected MultiSynth to incre- ment the output frequency by the Nx_FSTEPW parameter. See registers 0x0339–0x0358 0x001D FDEC 1 a rising edge will cause the selected MultiSynth to decre- ment the output frequency by the Nx_FSTEPW parameter.
  • Page 88 Si5345-44-42-D-RM Register 0x002C LOS Enable Reg Address Bit Field Type Name Description 0x002C LOS_EN 1 to enable LOS for a clock input; 0 for disable 0x002C LOSXAXB_DIS Enable LOS detection on the XAXB inputs. 0: Enable LOS Detection (default) 1: Disable LOS Detection Input 0 (IN0): LOS_EN[0] ...
  • Page 89 Si5345-44-42-D-RM Register 0x0030-0x0031 LOS1 Trigger Threshold Reg Address Bit Field Type Name Description 0x0030 LOS1_TRG_THR 16-bit Threshold Value 0x0031 15:8 LOS1_TRG_THR ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 1, given a particular frequency plan. Register 0x0032-0x0033 LOS2 Trigger Threshold Reg Address Bit Field Type...
  • Page 90 Si5345-44-42-D-RM ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 1, given a particular frequency plan. Register 0x003A-0x003B LOS2 Clear Threshold Reg Address Bit Field Type Name Description 0x003A LOS2_CLR_THR 16-bit Threshold Value 0x003B 15:8 LOS2_CLR_THR ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 2, given a particular frequency plan.
  • Page 91 Si5345-44-42-D-RM Register 0x0041-0x0045 OOF Divider Select Reg Address Bit Field Type Name Description 0x0041 OOF0_DIV_SEL Sets a divider for the OOF circuitry for each input clock 0,1,2,3. The divider value 0x0042 OOF1_DIV_SEL OOFx_DIV_SEL is 2 . CBPro sets these divid- 0x0043 OOF2_DIV_SEL ers.
  • Page 92 Si5345-44-42-D-RM Register 0x004E-0x04F OOF Detection Windows Reg Address Bit Field Type Setting Name Description 0x004E OOF0_DETWIN_SEL Values calculated by CBPro 0x004E OOF1_DETWIN_SEL 0x004F OOF2_DETWIN_SEL 0x004F OOF3_DETWIN_SEL Register 0x0051-0x0054 Fast Out of Frequency Set Threshold Reg Address Bit Field Type Name Description 0x0051 FAST_OOF0_SET_THR...
  • Page 93 Si5345-44-42-D-RM Register 0x005A-0x005D OOF0 Ratio for Reference Reg Address Bit Field Type Name Description 0x005A OOF0_RATIO_REF Values calculated by CBPro 0x005B 15:8 OOF0_RATIO_REF 0x005C 23:16 OOF0_RATIO_REF 0x005D 25:24 OOF0_RATIO_REF Register 0x005E-0x0061 OOF1 Ratio for Reference Reg Address Bit Field Type Name Description 0x005E...
  • Page 94 Si5345-44-42-D-RM Register 0x0093 Fast LOL Detection Window Reg Address Bit Field Type Name Description 0x0093 LOL_FST_DETWIN_SEL Values calculated by CBPro Register 0x0095 Fast LOL Detection Value Reg Address Bit Field Type Name Description 0x0095 LOL_FST_VALWIN_SEL Values calculated by CBPro Register 0x0096 Fast LOL Set Threshold Reg Address Bit Field Type...
  • Page 95 Si5345-44-42-D-RM Register 0x009E LOL Set Threshold Reg Address Bit Field Type Name Description 0x009E LOL_SET_THR Configures the loss of lock set thresholds. Select- able as 0.1, 0.3, 1, 3, 10, 30, 100, 300, 1000, 3000, 10000. Values are in ppm. The following are the thresholds for the value that is placed in the top four bits of register 0x009E.
  • Page 96 Si5345-44-42-D-RM Register 0x00A2 LOL Timer Enable Reg Address Bit Field Type Name Description 0x00A2 LOL_TIMER_EN 0 to disable 1 to enable LOL_TIMER_EN extends the time after LOL negates that the clock outputs can be disabled by LOL_CLR_DELAY (see below). Register 0x00A9-0x00AC LOL Clear Delay Reg Address Bit Field Type...
  • Page 97 Si5345-44-42-D-RM Register 0x00E5 Fastlock Extend Enable Reg Address Bit Field Type Name Description 0x00E5 FASTLOCK_EXTEND_EN Extend Fastlock bandwidth period past LOL Clear 0: Do not extend Fastlock period 1: Extend Fastlock period (default) Register 0x00EA-0x00ED LOL Detection Value Reg Address Bit Field Type Name...

  • Page 98: Registers Si5345

    Si5345-44-42-D-RM 14.3.2. Page 1 Registers Si5345 Register 0x0102 Global OE Gating for all Clock Output Drivers Reg Address Bit Field Type Name Description 0x0102 OUTALL_DISABLE_LOW 1 Pass through the output enables, 0 disables all output drivers Register 0x0108 Clock Output Driver 0 and R-Divider 0 Configuration Reg Address Bit Field Type...
  • Page 99 Si5345-44-42-D-RM Register 0x010A Output 0 Swing and Amplitude Reg Address Bit Field Type Name Description 0x010A OUT0_CM This field only applies when OUT0_FORMAT=1 or 2. See Table 26, “Settings for LVDS, LVPECL, and HCSL,” on page 42 and " Appendix A—Setting the Dif- ferential Output Driver to Non-Standard Amplitudes"...

  • Page 100: Table 46. Registers That Follow The Same Definitions Above

    Si5345-44-42-D-RM Table 46. Registers that Follow the Same Definitions Above Register Address Description (Same as) Address 0x010D Clock Output Driver 1 Config 0x0108 0x010E Clock Output Driver 1 Format, Sync 0x0109 0x010F Clock Output Driver 1 Ampl, CM 0x010A 0x0110 OUT1_MUX_SEL, OUT1_VDD_SEL_EN, OUT1_VDD_SEL, 0x010B OUT1_INV...
  • Page 101 Si5345-44-42-D-RM Table 46. Registers that Follow the Same Definitions Above (Continued) 0x0133 OUT8_MUX_SEL, OUT8_VDD_SEL_EN, OUT8_VDD_SEL, 0x010B OUT8_INV 0x013A Clock Output Driver 9 Config 0x0108 0x013B Clock Output Driver 9 Format, Sync 0x0109 0x013C Clock Output Driver 9 Ampl, CM 0x010A 0x013D OUT9_MUX_SEL, OUT9_VDD_SEL_EN, OUT9_VDD_SEL, 0x010B...
  • Page 102 Si5345-44-42-D-RM Register 0x0145 Power Down All Reg Address Bit Field Type Name Description 0x0145 OUT_PDN_ALL 0- no effect 1- all drivers powered down Register 0x0146-0x0147 Reg Address Bit Field Type Setting Name Description 0x0146 DRV_RST 0x0147 11:8 DRV_RST Rev. 1.0...

  • Page 103: Registers Si5345

    47:40 P0_NUM This set of registers configures the P-dividers which are located at the four input clocks seen in Figure 2, “Si5342 DSPLL and Multisynth System Flow Diagram,” on page 11. ClockBuilder Pro calculates the correct values for the P-dividers.

  • Page 104: Table 47. Registers That Follow The P0_Num And P0_Den Above

    32-bit Integer Number 0x020E-0x0211 This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 2, “Si5342 DSPLL and Multisynth System Flow Diagram,” on page 11. ClockBuilder Pro calculates the correct values for the P-dividers.
  • Page 105 Si5345-44-42-D-RM Register 0x0231 P0 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0231 P0_FRACN_MODE P0 (IN0) input divider fractional mode. Must be set to 0xB for proper operation. 0x0231 P0_FRAC_EN P0 (IN0) input divider fractional enable 0: Integer-only division. 1: Fractional (or Integer) division.
  • Page 106 Si5345-44-42-D-RM Register 0x0234 P3 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0234 P3_FRACN_MODE P3 (IN3) input divider fractional mode. Must be set to 0xB for proper operation. 0x0234 P3_FRAC_EN P3 (IN3) input divider fractional enable 0: Integer-only division. 1: Fractional (or Integer) division.

  • Page 107: Table 48. Registers That Follow The R0_Reg

    Si5345-44-42-D-RM Register 0x023F MXAXB Update Reg Address Bit Field Type Setting Name Description 0x023F MXAXB_UPDATE Set to 1 to update the MXAXB_NUM and MXAXB_DEN values. A SOFT_RST may also be used to update these values. Register 0x024A-0x024C R0 Divider Reg Address Bit Field Type Name...
  • Page 108 Si5345-44-42-D-RM Register 0x026B–0x0272 User Scratch Pad Reg Address Bit Field Type Name Description 0x026B DESIGN_ID0 ASCII encoded string defined by CBPro user, with user defined space 0x026C 15:8 DESIGN_ID1 or null padding of unused characters. 0x026D 23:16 DESIGN_ID2 A user will normally include a config- uration ID + revision ID.
  • Page 109 Si5345-44-42-D-RM Register 0x0278–0x027C OPN Identifier Reg Address Bit Field Type Name Description 0x0278 OPN_ID0 OPN unique identifier. ASCII encoded. For example, with OPN: 0x0279 15:8 OPN_ID1 5380C-A12345-GM, 12345 is the 0x027A 23:16 OPN_ID2 OPN unique identifier, which sets: OPN_ID0: 0x31 0x027B 31:24 OPN_ID3...
  • Page 110 Si5345-44-42-D-RM Register 0x0296 Reg Address Bit Field Type Name Description 0x0296 LOL_SLW_VALWIN_SELX Set by CBPro. Register 0x0297 Fastlock Delay on Input Switch Enable Reg Address Bit Field Type Name Description 0x0297 FASTLOCK_DLY_ONSW_EN Set by CBPro. Register 0x0299 Fastlock Delay on LOL Enable Reg Address Bit Field Type...

  • Page 111: Registers Si5345

    Si5345-44-42-D-RM 14.3.4. Page 3 Registers Si5345 Register 0x0302-0x0307 N0 Numerator Reg Address Bit Field Type Name Description 0x0302 N0_NUM 48-bit Integer Number 0x0303 15:8 N0_NUM 0x0304 23:16 N0_NUM 0x0305 31:24 N0_NUM 0x0306 39:32 N0_NUM 0x0307 43:40 N0_NUM The N dividers are interpolative dividers that are used as output dividers that feed into the R dividers. ClockBuilder Pro calculates the correct values for the N-dividers.

  • Page 112: Table 49. Registers That Follow The N0_Num And N0_Den Definitions

    Si5345-44-42-D-RM Table 49. Registers that Follow the N0_NUM and N0_DEN Definitions Register Address Description Size Same as Address 0x030D-0x0312 N1 Numerator 44-bit Integer Number 0x0302-0x0307 0x0313-0x0316 N1 Denominator 32-bit Integer Number 0x0308-0x030B 0x0317 N1_UPDATE one bit 0x030C 0x0318-0x031D N2 Numerator 44-bit Integer Number 0x0302-0x0307 0x031E-0x0321...

  • Page 113: Figure 55. Logic Diagram Of The Finc/Fdec Masks

    Si5345-44-42-D-RM FINC, 1Dh[0] (self clear) FDEC is the same as FINC FINC pin, pos edge trig NxFINC N_FSTEP_MSKx, 339h[4:0] Figure 55. Logic Diagram of the FINC/FDEC Masks Register 0x033B-0x0340 N0 Frequency Step Word Reg Address Bit Field Type Name Description 0x033B N0_FSTEPW 44-bit Integer Number...
  • Page 114 Si5345-44-42-D-RM Register 0x035B–0x035C Divider N1 Delay Control Reg Address Bit Field Type Name Description 0x035B N1_DELAY[7:0] Lower byte of N1_DELAY[15:0] 0x035C 15:8 N1_DELAY[15:8] Upper byte of N1_DELAY[15:0] N1_DELAY behaves in the same manner as N0_DELAY Register 0x035D–0x035E Divider N2 Delay Control Reg Address Bit Field Type...

  • Page 115: Registers Si5345

    Si5345-44-42-D-RM 14.3.5. Page 4 Registers Si5345 Register 0x0487 Zero Delay Mode Setup Reg Address Bit Field Type Name Description 0x0487 ZDM_EN 0 to disable ZD mode 1 to enable ZD mode 0x0487 ZDM_IN_SEL Clock input select when in ZD mode. 0 for IN0, 1 for IN1,2 for IN2, 3 reserved Note: In ZD mode the feedback clock...

  • Page 116: Registers Si5345

    Si5345-44-42-D-RM 14.3.6. Page 5 Registers Si5345 Register 0x0502 Reg Address Bit Field Type Name Description 0x0502 ADD_DIV256 Register 0x0508-0x050D Loop Bandwidth Reg Address Bit Field Type Name Description 0x0508 BW0_PLL PLL bandwidth parameter 0x0509 BW1_PLL PLL bandwidth parameter 0x050A BW2_PLL PLL bandwidth parameter 0x050B BW3_PLL...
  • Page 117 Si5345-44-42-D-RM Register 0x0515-0x051B M Divider Numerator, 56-bits Reg Address Bit Field Type Name Description 0x0515 M_NUM 56-bit Number 0x0516 15:8 M_NUM 0x0517 23:16 M_NUM 0x0518 31:24 M_NUM 0x0519 39:32 M_NUM 0x051A 47:40 M_NUM 0x051B 55:48 M_NUM Register 0x051C-0x051F M Divider Denominator, 32-bits Reg Address Bit Field Type...
  • Page 118 Si5345-44-42-D-RM Register 0x052A Input Clock Select Reg Address Bit Field Type Name Description 0x052A IN_SEL_REGCTRL 0 for pin controlled clock selection 1 for register controlled clock selection 0x052A IN_SEL 0 for IN0, 1 for IN1, 2 for IN2, 3 for IN3 (or FB_IN) Input clock selection for manual register based and pin controlled clock selection.
  • Page 119 Si5345-44-42-D-RM Register 0x052E Holdover History Average Length Reg Address Bit Field Type Name Description 0x052E HOLD_HIST_LEN 5-bit value The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length. The average frequency is then used as the holdover frequency. Register 0x052F Holdover History Delay Reg Address Bit Field...
  • Page 120 Si5345-44-42-D-RM Register 0x0536 Input Clock Switching Control Reg Address Bit Field Type Name Description 0x0536 CLK_SWTCH_MODE 0 = manual 1 = automatic/non-revertive 2 = automatic/revertive 3 = reserved 0x0536 HSW_EN 0 glitchless switching mode (phase buildout turned off) 1 hitless switching mode (phase build- out turned on) Register 0x0537 Input Alarm Masks Reg Address...
  • Page 121 Si5345-44-42-D-RM This register is used to assign a priority to an input clock for automatic clock input switching. The available clock with the lowest priority level will be selected. When input clocks are assigned the same priority, they will use the following default priority list: 0, 1, 2, 3.
  • Page 122 Si5345-44-42-D-RM Register 0x053D Reg Address Bit Field Type Name Description 0x053D HSW_COARSE_PM_LEN Set by CBPro. Register 0x053E Reg Address Bit Field Type Name Description 0x053E HSW_COARSE_PM_DLY Set by CBPro. Register 0x053F Reg Address Bit Field Type Name Description 0x053F HOLD_HIST_VALID 1 = there is enough historical fre- quency data collected for valid holdover.
  • Page 123 Si5345-44-42-D-RM Register 0x059D Holdover Exit BW Reg Address Bit Field Type Setting Name Description 0x059D HOLDEXIT_BW0 Set by CBPro to set the PLL bandwidth when exiting holdover, works with HOL- DEXIT_BW_SEL0 and HOLD_BW_SEL1 Register 0x059E Holdover Exit BW Reg Address Bit Field Type Setting Name...
  • Page 124 Si5345-44-42-D-RM Register 0x059A2 Holdover Exit BW Reg Address Bit Field Type Setting Name Description 0x05A2 HOLDEXIT_BW5 Set by CBPro to set the PLL bandwidth when exiting holdover, works with HOL- DEXIT_BW_SEL0 and HOLD_BW_SEL1 Register 0x05A6 Hitless Switching Control Reg Address Bit Field Type Setting Name...

  • Page 125: Registers Si5345

    Si5345-44-42-D-RM 14.3.7. Page 9 Registers Si5345 Register 0x090E XAXB Configuration Reg Address Bit Field Type Name Description 0x090E XAXB_EXTCLK_EN 0 to use a crystal at the XAXB pins 1 to use an external clock source at the XAXB pins Register 0x0943 Control I/O Voltage Select Reg Address Bit Field Type...
  • Page 126 Si5345-44-42-D-RM Register 0x094E-0x094F Input Clock Buffer Hysteresis Reg Address Bit Field Type Setting Name Description 0x094E REFCLK_HYS_SEL Value calculated in CBPro 0x094F REFCLK_HYS_SEL Register 0x095E MXAXB Fractional Mode Reg Address Bit Field Type Setting Name Description 0x094A INX_TO_PFD_EN Set to 1 by CBPro. Do not change. Rev.

  • Page 127: Page A Registers Si5345

    Si5345-44-42-D-RM 14.3.8. Page A Registers Si5345 Register 0x0A02 Enable N-divider 0.5x Reg Address Bit Field Type Setting Name Description 0x0A02 N_ADD_0P5 Value calculated in CBPro Register 0x0A03 Output Multisynth Clock to Output Driver Reg Address Bit Field Type Name Description 0x0A03 N_CLK_TO_OUTX_EN Routes Multisynth outputs to output driver muxes.

  • Page 128: Page B Registers Si5345

    Si5345-44-42-D-RM 14.3.9. Page B Registers Si5345 Register 0x0B44 Output Multisynth Clock to Output Driver Reg Address Bit Field Type Name Description 0x0B44 PDIV_FRACN_CLK_DIS Disable digital clocks to input P (IN0–3) fractional dividers. 0x0B44 FRACN_CLK_DIS_PLL Disable digital clock to M fractional divider. Register 0x0B46 Reg Address Bit Field...

  • Page 129: Si5344 Register Definitions

    Si5345-44-42-D-RM 14.4. Si5344 Register Definitions 14.4.1. Page 0 Registers Si5344 Register 0x0000 Die Rev Reg Address Bit Field Type Name Description 0x0000 DIE_REV 4- bit Die Revision Number Register 0x0001 Page Reg Address Bit Field Type Name Description 0x0001 PAGE Selects one of 256 possible pages.
  • Page 130 Si5345-44-42-D-RM Register 0x0006–0x0008 TOOL_VERSION Reg Address Bit Field Type Name Description 0x0006 TOOL_VERSION[3:0] Special 0x0006 TOOL_VERSION[7:4] Revision 0x0007 TOOL_VERSION[15:8] Minor[7:0] 0x0008 TOOL_VERSION[15:8] Minor[8] 0x0008 TOOL_VERSION[16] Major 0x0008 TOOL_VERSION[13:17] Tool. 0 for ClockBuilder Pro The software tool version that created the register values that are downloaded at power up is represented by TOOL_VERSION.
  • Page 131 Si5345-44-42-D-RM Register 0x000C Internal Status Bits Reg Address Bit Field Type Name Description 0x000C SYSINCAL 1 if the device is calibrating. 0x000C LOSXAXB 1 if there is no signal at the XAXB pins. 0x000C 0x000C 0x000C 0x000C SMBUS_TIMEOUT 1 if there is an SMBus timeout error. Bit 1 is the LOS status monitor for the XTAL or REFCLK at the XA/XB pins.
  • Page 132 Si5345-44-42-D-RM Register 0x0011 Sticky versions of Internal Status Bits Reg Address Bit Field Type Name Description 0x0011 SYSINCAL_FLG Sticky version of SYSINCAL 0x0011 LOSXAXB_FLG Sticky version of LOSXAXB 0x0011 0x0011 0x0011 0x0011 SMBUS_TIMEOUT_FLG Sticky version of SMBUS_TIMEOUT These are sticky flag bits. They are cleared by writing zero to the bit that has been set. Register 0x0012 Sticky OOF and LOS Flags Reg Address Bit Field...
  • Page 133 Si5345-44-42-D-RM Register 0x0017 Status Flag Masks Reg Address Bit Field Type Name Description 0x0017 SYSINCAL_INTR_MSK 1 to mask SYSINCAL_FLG from caus- ing an interrupt 0x0017 LOSXAXB_FLG_MSK 1 to mask the LOSXAXB_FLG from causing an interrupt 0x0017 SMBUS_TIMEOUT_INTR_MSK 1 to mask SMBUS_TIMEOUT_FLG from the interrupt These are the interrupt mask bits for the fault flags in register 0x0011.

  • Page 134: Figure 56. Logic Diagram Of The Finc/Fdec Masks

    Si5345-44-42-D-RM Register 0x001C Soft Reset and Calibration Reg Address Bit Field Type Name Description 0x001C SOFT_RST_ALL 1 Initialize and calibrates the entire device 0 No effect 0x001C SOFT_RST 0x001C SOFTCAL These bits are of type “S”, which is self-clearing. Register 0x001D FINC, FDEC Reg Address Bit Field Type...
  • Page 135 Si5345-44-42-D-RM Register 0x002B SPI 3 vs 4 Wire Reg Address Bit Field Type Name Description 0x002B SPI_3WIRE 0 for 4-wire SPI, 1 for 3-wire SPI 0x002B AUTO_NDIV_UPDATE Register 0x002C LOS Enable Reg Address Bit Field Type Name Description 0x002C LOS_EN 1 to enable LOS for a clock input;...
  • Page 136 Si5345-44-42-D-RM ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 0, given a particular frequency plan. Register 0x0030-0x0031 LOS1 Trigger Threshold Reg Address Bit Field Type Name Description 0x0030 LOS1_TRG_THR 16-bit Threshold Value 0x0031 15:8 LOS1_TRG_THR ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 1, given a particular frequency plan.
  • Page 137 Si5345-44-42-D-RM Register 0x0038-0x0039 LOS1 Clear Threshold Reg Address Bit Field Type Name Description 0x0038 LOS1_CLR_THR 16-bit Threshold Value 0x0039 15:8 LOS1_CLR_THR ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 1, given a particular frequency plan. Register 0x003A-0x003B LOS2 Clear Threshold Reg Address Bit Field Type...
  • Page 138 Si5345-44-42-D-RM Register 0x0040 OOF Reference Select Reg Address Bit Field Type Name Description 0x0040 OOF_REF_SEL 0 for CLKIN0 1 for CLKIN1 2 for CLKIN2 3 for CLKIN3 4 for XAXB Register 0x0041-0x0045 OOF Divider Select Reg Address Bit Field Type Name Description 0x0041...
  • Page 139 Si5345-44-42-D-RM Register 0x004A-0x004D Out of Frequency Clear Threshold Reg Address Bit Field Type Name Description 0x004A OOF0_CLR_THR OOF Clear threshold. Range is up to  500 ppm in steps of 1/16 ppm 0x004B OOF1_CLR_THR OOF Clear threshold. Range is up to ...
  • Page 140 Si5345-44-42-D-RM These registers determine the OOF alarm clear threshold for IN3, IN2, IN1 and IN0 when the fast control is enabled. The value in each of the register is (1+ value)*1000 ppm. ClockBuilder Pro is used to determine the values for these registers. OOF needs a frequency reference.
  • Page 141 Si5345-44-42-D-RM Register 0x0066-0x0069 OOF3 Ratio for Reference Reg Address Bit Field Type Name Description 0x0066 OOF3_RATIO_REF Values calculated by CBPro 0x0067 15:8 OOF3_RATIO_REF 0x0068 23:16 OOF3_RATIO_REF 0x0069 25:24 OOF3_RATIO_REF Register 0x0092 Fast LOL Enable Reg Address Bit Field Type Name Description 0x0092 LOL_FST_EN...
  • Page 142 Si5345-44-42-D-RM Register 0x009A LOL Enable Reg Address Bit Field Type Name Description 0x009A LOL_SLOW_EN_PLL 1 to enable LOL; 0 to disable LOL. ClockBuilder Pro provides the LOL register values for a particular frequency plan. Register 0x009B Slow LOL Detection Window Reg Address Bit Field Type...
  • Page 143 Si5345-44-42-D-RM Register 0x00A0 LOL Clear Threshold Reg Address Bit Field Type Name Description 0x00A0 LOL_CLR_THR Configures the loss of lock set thresholds. Selectable as 0.1, 0.3, 1, 3, 10, 30, 100, 300, 1000, 3000, 10000. Values are in ppm. The following are the thresholds for the value that is placed in the top four bits of register 0x00A0. ClockBuilder Pro sets these values.
  • Page 144 Si5345-44-42-D-RM Register 0x00E2 Reg Address Bit Field Type Name Description 0x00E2 ACTIVE_NVM_BANK Read-only field indicating number of user bank writes caried out so far. Value Description zero three Register 0x00E3 Reg Address Bit Field Type Setting Name Description 0x00E3 NVM_WRITE Write 0xC7 to initiate an NVM bank burn.

  • Page 145: Registers Si5344

    Si5345-44-42-D-RM 14.4.2. Page 1 Registers Si5344 Register 0x0102 Global OE Gating for all Clock Output Drivers Reg Address Bit Field Type Name Description 0x0102 OUTALL_DISABLE_LOW 1 Pass through the output enables, 0 disables all output drivers Register 0x0112 Clock Output Driver 0 and R-Divider 0 Configuration Reg Address Bit Field Type...
  • Page 146 Si5345-44-42-D-RM Register 0x0114 Output 0 Swing and Amplitude Reg Address Bit Field Type Name Description 0x0114 OUT0_CM Output common mode voltage adjustment Programmable swing mode with normal swing configu- ration: Step size = 100 mV Range = 0.9 V to 2.3 V if VDDO = 3.3 V Range = 0.6 V to 1.5V if VDDO = 2.5 V Range=0.5 V to 0.9 V if VDDO = 1.8 V Programmable swing mode with high0 swing configu-...

  • Page 147: Table 51. Registers That Follow The Same Definitions Above

    Si5345-44-42-D-RM Register 0x0115 R-Divider 0 Mux Selection Reg Address Bit Field Type Name Description 0x0115 OUT0_MUX_SEL Output driver 0 input mux select.This selects the source of the multisynth. 0: MS0 1: MS1 2: MS2 3: MS3 4: MS4 5: reserved 6: reserved 7: reserved 0x0115...
  • Page 148 Si5345-44-42-D-RM Register 0x013F-0x0140 Reg Address Bit Field Type Setting Name Description 0x013F OUTX_ALWAYS_ON 0x0140 11:8 OUTX_ALWAYS_ON Register 0x0141 Output Disable Mask for LOS XAXB Reg Address Bit Field Type Setting Name Description 0x0141 OUT_DIS_MSK 0x0141 OUT_DIS_LOL_MSK 0x0141 OUT_DIS_MSK_LOSXAXB Determines if outputs are disabled during an LOSXAXB condition.
  • Page 149 Si5345-44-42-D-RM Register 0x0146-0x0147 Reg Address Bit Field Type Setting Name Description 0x0146 DRV_RST 0x0147 11:8 DRV_RST Register 0x0148-0x0149 Reg Address Bit Field Type Setting Name Description 0x0148 DRV_DIV_RST 0x0149 11:8 DRV_DIV_RST Rev. 1.0...

  • Page 150: Registers Si5344

    47:40 P0_NUM This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 2, “Si5342 DSPLL and Multisynth System Flow Diagram,” on page 11. ClockBuilder Pro calculates the correct values for the P-dividers.

  • Page 151: Table 52. Registers That Follow The P0_Num And P0_Den

    32-bit Integer Number 0x020E-0x0211 This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 2, “Si5342 DSPLL and Multisynth System Flow Diagram,” on page 11. ClockBuilder Pro calculates the correct values for the P-dividers.
  • Page 152 Si5345-44-42-D-RM Register 0x0231 P0 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0231 P0_FRACN_MODE P0 (IN0) input divider fractional mode. Must be set to 0xB for proper operation. 0x0231 P0_FRAC_EN P0 (IN0) input divider fractional enable 0: Integer-only division. 1: Fractional (or Integer) division.
  • Page 153 Si5345-44-42-D-RM Register 0x0234 P3 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0234 P3_FRACN_MODE P3 (IN3) input divider fractional mode. Must be set to 0xB for proper operation. 0x0234 P3_FRAC_EN P3 (IN3) input divider fractional enable 0: Integer-only division. 1: Fractional (or Integer) division.

  • Page 154: Table 53. Registers That Follow The R0_Reg

    Si5345-44-42-D-RM Register 0x023F MXAXB Update Reg Address Bit Field Type Setting Name Description 0x023F MXAXB_UPDATE Set to 1 to update the MXAXB_NUM and MXAXB_DEN values. A SOFT_RST may also be used to update these values. Register 0x0250-0x0252 R0 Divider Reg Address Bit Field Type Name...
  • Page 155 Si5345-44-42-D-RM Register 0x0278-0x027C OPN Identifier Reg Address Bit Field Type Name Description 0x0278 OPN_ID0 OPN unique identifier. ASCII encoded. For example, with OPN: 0x0279 15:8 OPN_ID1 5344C-A12345-GM, 12345 is the 0x027A 23:16 OPN_ID2 OPN unique identifier, which sets: OPN_ID0: 0x31 0x027B 31:24 OPN_ID3...
  • Page 156 Si5345-44-42-D-RM Register 0x0296 Reg Address Bit Field Type Name Description 0x0296 LOL_SLW_VALWIN_SELX Set by CBPro. Register 0x0297 Fastlock Delay on Input Switch Enable Reg Address Bit Field Type Name Description 0x0297 FASTLOCK_DLY_ONSW_EN Set by CBPro. Register 0x0299 Fastlock Delay on LOL Enable Reg Address Bit Field Type...

  • Page 157: Registers Si5344

    Si5345-44-42-D-RM 14.4.4. Page 3 Registers Si5344 Register 0x0302-0x0307 N0 Numerator Reg Address Bit Field Type Name Description 0x0302 N0_NUM 44-bit Integer Number The N0 value is N0_NUM/N0_DEN 0x0303 15:8 N0_NUM 0x0304 23:16 N0_NUM 0x0305 31:24 N0_NUM 0x0306 39:32 N0_NUM 0x0307 43:40 N0_NUM The N dividers are interpolative dividers that are used as output dividers that feed into the R dividers.

  • Page 158: Table 55. Registers That Follow The N0_Fstepw Definition

    Si5345-44-42-D-RM Register 0x0338 Global N Divider Update Reg Address Bit Field Type Name Description 0x0338 N_UPDATE Set this bit to update all five N dividers. This bit is provided so that all of the divider bits can be changed at the same time. First, write all of the new values to the divider, then set the update bit.
  • Page 159 Si5345-44-42-D-RM Register 0x0359–0x35A N0 Delay Control Reg Address Bit Field Type Name Description 0x0359 N0_DELAY[7:0] Lower byte of N0_DELAY[15:0] 0x035A N0_DELAY[15:8] Upper byte of N0_DELAY[15:0] Nx_DELAY[15:0] is a 2s complement number that sets the output delay of MultiSynthx. The delay in seconds is Nx_DELAY/(256 x Fvco) where Fvco is the VCO frequency in Hz. The maximum positive and negative delay is ±(2 –1)/(256 x Fvco).

  • Page 160: Registers Si5344

    Si5345-44-42-D-RM 14.4.5. Page 4 Registers Si5344 Register 0x0487 Zero Delay Mode Setup Reg Address Bit Field Type Name Description 0x0487 ZDM_EN 0 to disable ZD mode 1 to enable ZD mode 0x0487 ZDM_IN_SEL Clock input select when in ZD mode. 0 for IN0, 1 for IN1,2 for IN2, 3 reserved Note: In ZD mode the feedback clock...

  • Page 161: Registers Si5344

    Si5345-44-42-D-RM 14.4.6. Page 5 Registers Si5344 Register 0x0502 Reg Address Bit Field Type Name Description 0x0502 ADD_DIV256 Register 0x0508-0x050D Loop Bandwidth Reg Address Bit Field Type Name Description 0x0508 BW0_PLL PLL bandwidth parameter 0x0509 BW1_PLL PLL bandwidth parameter 0x050A BW2_PLL PLL bandwidth parameter 0x050B BW3_PLL...
  • Page 162 Si5345-44-42-D-RM Register 0x0515-0x051B M Divider Numerator, 56-bits Reg Address Bit Field Type Name Description 0x0515 M_NUM 56-bit Number 0x0516 15:8 M_NUM 0x0517 23:16 M_NUM 0x0518 31:24 M_NUM 0x0519 39:32 M_NUM 0x051A 47:40 M_NUM 0x051B 55:48 M_NUM Register 0x051C-0x051F M Divider Denominator, 32-bits Reg Address Bit Field Type...
  • Page 163 Si5345-44-42-D-RM Register 0x052A Input Clock Select Reg Address Bit Field Type Name Description 0x052A IN_SEL_REGCTRL 0 for pin controlled clock selection 1 for register controlled clock selection 0x052A IN_SEL 0 for IN0, 1 for IN1, 2 for IN2, 3 for IN3 (or FB_IN) Input clock selection for manual register based and pin controlled clock selection.
  • Page 164 Si5345-44-42-D-RM Register 0x052E Holdover History Average Length Reg Address Bit Field Type Name Description 0x052E HOLD_HIST_LEN 5-bit value The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length. The average frequency is then used as the holdover frequency. Register 0x052F Holdover History Delay Reg Address Bit Field...
  • Page 165 Si5345-44-42-D-RM Register 0x0536 Input Clock Switching Control Reg Address Bit Field Type Name Description 0x0536 CLK_SWTCH_MODE 0 = manual 1 = automatic/non-revertive 2 = automatic/revertive 3 = reserved 0x0536 HSW_EN 0 glitchless switching mode (phase buildout turned off) 1 hitless switching mode (phase build- out turned on) Register 0x0537 Input Alarm Masks Reg Address...
  • Page 166 Si5345-44-42-D-RM This register is used to assign a priority to an input clock for automatic clock input switching. The available clock with the lowest priority level will be selected. When input clocks are assigned the same priority, they will use the following default priority list: 0, 1, 2, 3.
  • Page 167 Si5345-44-42-D-RM Register 0x053D Reg Address Bit Field Type Name Description 0x053D HSW_COARSE_PM_LEN Set by CBPro. Register 0x053E Reg Address Bit Field Type Name Description 0x053E HSW_COARSE_PM_DLY Set by CBPro. Register 0x053F Reg Address Bit Field Type Name Description 0x053F HOLD_HIST_VALID 1 = there is enough historical fre- quency data collected for valid holdover.
  • Page 168 Si5345-44-42-D-RM Register 0x059D Holdover Exit BW Reg Address Bit Field Type Setting Name Description 0x059D HOLDEXIT_BW0 Set by CBPro to set the PLL bandwidth when exiting holdover, works with HOL- DEXIT_BW_SEL0 and HOLD_BW_SEL1 Register 0x059E Holdover Exit BW Reg Address Bit Field Type Setting Name...
  • Page 169 Si5345-44-42-D-RM Register 0x059A2 Holdover Exit BW Reg Address Bit Field Type Setting Name Description 0x05A2 HOLDEXIT_BW5 Set by CBPro to set the PLL bandwidth when exiting holdover, works with HOL- DEXIT_BW_SEL0 and HOLD_BW_SEL1 Register 0x05A6 Hitless Switching Control Reg Address Bit Field Type Setting Name Description...

  • Page 170: Registers Si5344

    Si5345-44-42-D-RM 14.4.7. Page 9 Registers Si5344 Register 0x090E XAXB Configuration Reg Address Bit Field Type Name Description 0x090E XAXB_EXTCLK_EN 0 to use a crystal at the XAXB pins 1 to use an external clock source at the XAXB pins Register 0x0943 Control I/O Voltage Select Reg Address Bit Field Type...
  • Page 171 Si5345-44-42-D-RM Register 0x094E-0x094F Input Clock Buffer Hysteresis Reg Address Bit Field Type Setting Name Description 0x094E REFCLK_HYS_SEL Value calculated in CBPro 0x094F REFCLK_HYS_SEL Register 0x095E MXAXB Fractional Mode Reg Address Bit Field Type Setting Name Description 0x094A INX_TO_PFD_EN Set to 1 by CBPro. Do not change. Rev.

  • Page 172: Page A Registers Si5344

    Si5345-44-42-D-RM 14.4.8. Page A Registers Si5344 Register 0x0A02 Output Multisynth Integer Divide Mode Reg Address Bit Field Type Name Description 0x0A02 N_ADD_0P5 Value calculated in CBPro Register 0x0A03 Output Multisynth Clock to Output Driver Reg Address Bit Field Type Name Description 0x0A03 N_CLK_TO_OUTX_EN Routes Multisynth outputs to output...

  • Page 173: Page B Registers Si5344

    Si5345-44-42-D-RM 14.4.9. Page B Registers Si5344 Register 0x0B44 Output Multisynth Clock to Output Driver Reg Address Bit Field Type Name Description 0x0B44 PDIV_FRACN_CLK_DIS Disable digital clocks to input P (IN0–3) frac- tional dividers. 0x0B44 FRACN_CLK_DIS_PLL Disable digital clock to M fractional divider. Register 0x0B46 Reg Address Bit Field...

  • Page 174: Si5342 Register Definitions

    Si5345-44-42-D-RM 14.5. Si5342 Register Definitions 14.5.1. Page 0 Registers Si5342 Register 0x0000 Die Rev Reg Address Bit Field Type Name Description 0x0000 DIE_REV 4- bit Die Revision Number Register 0x0001 Page Reg Address Bit Field Type Name Description 0x0001 PAGE Selects one of 256 possible pages.
  • Page 175 ClockBuilder Pro project file. Si5342C-A-GM. Applies to a “base” or “non-custom” OPN device. Base devices are factory pre-programmed to a specific base part type (e.g., Si5342 but exclude any user-defined frequency plan or other user-defined operating characteristics selected in ClockBuilder Pro. Rev. 1.0...
  • Page 176 Si5345-44-42-D-RM Register 0x000B I2C Address Reg Address Bit Field Type Setting Name Description 0x000B I2C_ADDR The upper 5 bits of the 7 bit I C address. The lower 2 bits are controlled by the A1 and A0 pins. Register 0x000C Internal Status Bits Reg Address Bit Field Type...
  • Page 177 Si5345-44-42-D-RM Register 0x000F Calibration Status Reg Address Bit Field Type Name Description 0x000F CAL_PLL 1 if the DSPLL internal calibration is busy This status bit indicates if a DSPLL is currently busy with calibration. This bit is not sticky. Register 0x0011 Sticky versions of Internal Status Bits Reg Address Bit Field Type...
  • Page 178 Si5345-44-42-D-RM Register 0x0014 Sticky INCAL Flag Reg Address Bit Field Type Name Description 0x0014 CAL_FLG_PLL 1 if the internal calibration was busy This bit is the sticky flag version of 0x000F. This bit is cleared by writing 0 to bit 5. Register 0x0017 Status Flag Masks Reg Address Bit Field...

  • Page 179: Figure 57. Finc, Fdec Logic Diagram

    Si5345-44-42-D-RM These are the interrupt mask bits for the LOL and HOLD flags in register 0x0013. If a mask bit is set the alarm will be blocked from causing an interrupt. Register 0x001A INCAL Mask Reg Address Bit Field Type Name Description 0x001A...
  • Page 180 Si5345-44-42-D-RM Register 0x001E Sync, Power Down and Hard Reset Reg Address Bit Field Type Name Description 0x001E 1 to put the device into low power mode 0x001E HARD_RST 1 causes hard reset. The same as power up except that the serial port access is not held at reset. This does not self-clear, so after setting the bit it must be cleared.
  • Page 181 Si5345-44-42-D-RM Register 0x002D Loss of Signal Re-Qualification Value Reg Address Bit Field Type Name Description 0x002D LOS0_VAL_TIME Clock Input 0 0 for 2 msec 1 for 100 msec 2 for 200 msec 3 for one second 0x002D LOS1_VAL_TIME Clock Input 1, same as above 0x002D LOS2_VAL_TIME Clock Input 2, same as above...
  • Page 182 Si5345-44-42-D-RM Register 0x0034-0x0035 LOS3 Trigger Threshold Reg Address Bit Field Type Name Description 0x0034 LOS3_TRG_THR 16-bit Threshold Value 0x0035 15:8 LOS3_TRG_THR ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 3, given a particular frequency plan. Register 0x0036-0x0037 LOS0 Clear Threshold Reg Address Bit Field Type...
  • Page 183 Si5345-44-42-D-RM ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 3, given a particular frequency plan. Register 0x003F OOF Enable Reg Address Bit Field Type Name Description 0x003F OOF_EN 1 to enable, 0 to disable 0x003F FAST_OOF_EN 1 to enable, 0 to disable Input 0 corresponds to OOF_EN [0], FAST_OOF_EN [4] ...
  • Page 184 Si5345-44-42-D-RM Register 0x0046-0x0049 Out of Frequency Set Threshold Reg Address Bit Field Type Name Description 0x0046 OOF0_SET_THR OOF Set threshold. Range is up to  500 ppm in steps of 1/16 ppm. 0x0047 OOF1_SET_THR OOF Set threshold. Range is up to ...
  • Page 185 Si5345-44-42-D-RM These registers determine the OOF alarm set threshold for IN3, IN2, IN1 and IN0 when the fast control is enabled. The value in each of the register is (1+ value) x 1000 ppm. ClockBuilder Pro is used to determine the values for these registers.
  • Page 186 Si5345-44-42-D-RM Register 0x0062-0x0065 OOF2 Ratio for Reference Reg Address Bit Field Type Name Description 0x0062 OOF2_RATIO_REF Values calculated by CBPro 0x0063 15:8 OOF2_RATIO_REF 0x0064 23:16 OOF2_RATIO_REF 0x0065 25:24 OOF2_RATIO_REF Register 0x0066-0x0069 OOF3 Ratio for Reference Reg Address Bit Field Type Name Description 0x0066...
  • Page 187 Si5345-44-42-D-RM Register 0x0098 Fast LOL Clear Threshold Reg Address Bit Field Type Name Description 0x0098 LOL_FST_CLR_THR_SEL Values calculated by CBPro Register 0x009A LOL Enable Reg Address Bit Field Type Name Description 0x009A LOL_SLOW_EN_PLL 1 to enable LOL; 0 to disable LOL. ClockBuilder Pro provides the LOL register values for a particular frequency plan.
  • Page 188 Si5345-44-42-D-RM The following are the thresholds for the value that is placed in the top four bits of register 0x009E. 0 = 0.1 ppm  1 = 0.3 ppm  2 = 1 ppm  3 = 3 ppm  4 = 10 ppm ...
  • Page 189 Si5345-44-42-D-RM Register 0x00A9-0x00AC LOL Clear Delay Reg Address Bit Field Type Name Description 0x00A9 LOL_CLR_DLY 29-bit value. Sets the clear timer for LOL. CBPro sets this value. 0x00AA 15:8 LOL_CLR_DLY 0x00AB 23:16 LOL_CLR_DLY 0x00AC 28:24 LOL_CLR_DLY The LOL Clear Delay value is set by ClockBuilder Pro. Register 0x00E2 Reg Address Bit Field...
  • Page 190 Si5345-44-42-D-RM Register 0x00EA-0x00ED LOL Detection Value Reg Address Bit Field Type Name Description 0x00EA FASTLOCK_EXTEND 29-bit value. Set by CBPro to minimize the phase transients when switching the PLL 0x00EB 15:8 FASTLOCK_EXTEND bandwidth. 0x00EC 23:16 FASTLOCK_EXTEND See FASTLOCK_EXTEND_SCL. 0x00ED 28:24 FASTLOCK_EXTEND Rev.

  • Page 191: Registers Si5342

    Si5345-44-42-D-RM 14.5.2. Page 1 Registers Si5342 Register 0x0102 Global OE Gating for all Clock Output Drivers Reg Address Bit Field Type Name Description 0x0102 OUTALL_DISABLE_LOW 1 Pass through the output enables, 0 disables all output drivers Register 0x0112 Clock Output Driver 0 and R-Divider 0 Configuration...
  • Page 192 Si5345-44-42-D-RM Register 0x0114 Output 0 Swing and Amplitude Reg Address Bit Field Type Name Description 0x0114 OUT0_CM Output common mode voltage adjustment Programmable swing mode with normal swing configu- ration: Step size = 100 mV Range = 0.9 V to 2.3 V if VDDO = 3.3 V Range = 0.6 V to 1.5V if VDDO=2.5 V Range = 0.5 V to 0.9V if VDDO=1.8 V Programmable swing mode with high0 swing configu-...

  • Page 193: Table 56. Registers That Follow The Same Definition As Above

    Si5345-44-42-D-RM Register 0x0115 R-Divider 0 Mux Selection Reg Address Bit Field Type Name Description 0x0115 OUT0_MUX_SEL Output driver 0 input mux select.This selects the source of the multisynth. 0: N0 1: N1 2: reserved 3: reserved 4: reserved 5: reserved 6: reserved 7: reserved 0x0115...
  • Page 194 Si5345-44-42-D-RM Register 0x0141 Output Disable Mask for LOS XAXB Reg Address Bit Field Type Setting Name Description 0x0141 OUT_DIS_MSK 0x0141 OUT_DIS_LOL_MSK 0x0141 OUT_DIS_MSK_LOSXAXB Determines if outputs are disabled during an LOSXAXB condition. 0: All outputs disabled on LOSXAXB 1: All outputs remain enabled during LOSXAXB condition 0x0141 OUT_DIS_MSK_LOS_PFD...

  • Page 195: Registers Si5342

    47:40 P0_NUM This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 2, “Si5342 DSPLL and Multisynth System Flow Diagram,” on page 11. ClockBuilder Pro calculates the correct values for the P-dividers.

  • Page 196: Table 57. Registers That Follow The P0_Num And P0_Den Definitions

    32-bit Integer Number 0x020E-0x0211 This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 2, “Si5342 DSPLL and Multisynth System Flow Diagram,” on page 11. ClockBuilder Pro calculates the correct values for the P-dividers.
  • Page 197 Si5345-44-42-D-RM Register 0x0231 P0 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0231 P0_FRACN_MODE P0 (IN0) input divider fractional mode. Must be set to 0xB for proper operation. 0x0231 P0_FRAC_EN P0 (IN0) input divider fractional enable 0: Integer-only division. 1: Fractional (or Integer) division.
  • Page 198 Si5345-44-42-D-RM Register 0x0234 P3 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0234 P3_FRACN_MODE P3 (IN3) input divider fractional mode. Must be set to 0xB for proper operation. 0x0234 P3_FRAC_EN P3 (IN3) input divider fractional enable 0: Integer-only division. 1: Fractional (or Integer) division.

  • Page 199: Table 58. Registers That Follow The R0_Reg

    Si5345-44-42-D-RM Register 0x023F MXAXB Update Reg Address Bit Field Type Setting Name Description 0x023F MXAXB_UPDATE Set to 1 to update the MXAXB_NUM and MXAX- B_DEN values. A SOFT_RST may also be used to update these values. Register 0x0250-0x0252 R0 Divider Reg Address Bit Field Type...
  • Page 200 ClockBuilder Pro project file. Si5342C-A-GM. Applies to a “base” or “non-custom” OPN device. Base devices are factory pre-programmed to a specific base part type (e.g., Si5342 but exclude any user-defined frequency plan or other user-defined operating characteristics selected in ClockBuilder Pro. Register 0x027D...
  • Page 201 Si5345-44-42-D-RM Register 0x0296 Fastlock Delay on Input Switch Reg Address Bit Field Type Name Description 0x0296 LOL_SLW_VALWIN_SELX Set by CBPro. Register 0x0297 Fastlock Delay on Input Switch Enable Reg Address Bit Field Type Name Description 0x0297 FASTLOCK_DLY_ONSW_EN Set by CBPro. Register 0x0299 Fastlock Delay on LOL Enable Reg Address Bit Field...

  • Page 202: Registers Si5342

    Si5345-44-42-D-RM 14.5.4. Page 3 Registers Si5342 Register 0x0302-0x0307 N0 Numerator Reg Address Bit Field Type Name Description 0x0302 N0_NUM 44-bit Integer Number 0x0303 15:8 N0_NUM 0x0304 23:16 N0_NUM 0x0305 31:24 N0_NUM 0x0306 39:32 N0_NUM 0x0307 43:40 N0_NUM The N dividers are interpolative dividers that are used as output dividers that feed into the R dividers. ClockBuilder Pro calculates the correct values for the N-dividers.

  • Page 203: Table 60. Registers That Follow The N0_Fstepw Definition

    Si5345-44-42-D-RM Register 0x0317 Reg Address Bit Field Type Name Description 0x0317 N1_UPDATE Set this bit to update the N1 divider This bit is provided so that all of the N1 divider bits can be changed at the same time. First, write all of the new values to the divider, then set the update bit.

  • Page 204: Table 61. Registers That Follow The N0_Delay Definition

    Si5345-44-42-D-RM Register 0x0359–0x035A N0 Delay Control Reg Address Bit Field Type Name Description 0x0359 N0_DELAY[7:0] 8-bit Integer delay portion 0x035A N0_DELAY[7:0] Upper byte of N0_DELAY[15:0] Nx_DELAY[15:0] is a 2s complement number that sets the output delay of MultiSynthx. The delay in seconds is Nx_DELAY/(256 x Fvco) where Fvco is the VCO frequency in Hz. The maximum positive and negative delay is ±(215–...

  • Page 205: Registers Si5342

    Si5345-44-42-D-RM 14.5.5. Page 4 Registers Si5342 Register 0x0487 Zero Delay Mode Setup Reg Address Bit Field Type Name Description 0x0487 ZDM_EN 0 to disable ZD mode 1 to enable ZD mode 0x0487 ZDM_IN_SEL Clock input select when in ZD mode.

  • Page 206: Registers Si5342

    Si5345-44-42-D-RM 14.5.6. Page 5 Registers Si5342 Register 0x0502 Reg Address Bit Field Type Name Description 0x0502 ADD_DIV256 Register 0x0508-0x050D Loop Bandwidth Reg Address Bit Field Type Name Description 0x0508 BW0_PLL PLL bandwidth parameter 0x0509 BW1_PLL PLL bandwidth parameter 0x050A BW2_PLL...
  • Page 207 Si5345-44-42-D-RM Register 0x0515-0x051B M Divider Numerator, 56-bits Reg Address Bit Field Type Name Description 0x0515 M_NUM 56-bit Number 0x0516 15:8 M_NUM 0x0517 23:16 M_NUM 0x0518 31:24 M_NUM 0x0519 39:32 M_NUM 0x051A 47:40 M_NUM 0x051B 55:48 M_NUM Register 0x051C-0x051F M Divider Denominator, 32-bits Reg Address Bit Field Type...
  • Page 208 Si5345-44-42-D-RM Register 0x052A Input Clock Select Reg Address Bit Field Type Name Description 0x052A IN_SEL_REGCTRL 0 for pin controlled clock selection 1 for register controlled clock selection 0x052A IN_SEL 0 for IN0, 1 for IN1, 2 for IN2, 3 for IN3 (or FB_IN) Input clock selection for manual register based and pin controlled clock selection.
  • Page 209 Si5345-44-42-D-RM Register 0x052E Holdover History Average Length Reg Address Bit Field Type Name Description 0x052E HOLD_HIST_LEN 5-bit value The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length. The average frequency is then used as the holdover frequency. Register 0x0531 Reg Address Bit Field...
  • Page 210 Si5345-44-42-D-RM Register 0x0536 Input Clock Switching Control Reg Address Bit Field Type Name Description 0x0536 CLK_SWTCH_MODE 0 = manual 1 = automatic/non-revertive 2 = automatic/revertive 3 = reserved 0x0536 HSW_EN 0 glitchless switching mode (phase buildout turned off) 1 hitless switching mode (phase build- out turned on) Register 0x0537 Input Alarm Masks Reg Address...
  • Page 211 Si5345-44-42-D-RM This register is used to assign a priority to an input clock for automatic clock input switching. The available clock with the lowest priority level will be selected. When input clocks are assigned the same priority, they will use the following default priority list: 0, 1, 2, 3.
  • Page 212 Si5345-44-42-D-RM Register 0x053D Reg Address Bit Field Type Name Description 0x053D HSW_COARSE_PM_LEN Set by CBPro. Register 0x053E Reg Address Bit Field Type Name Description 0x053E HSW_COARSE_PM_DLY Set by CBPro. Register 0x053F Reg Address Bit Field Type Name Description 0x053F HOLD_HIST_VALID 1 = there is enough historical fre- quency data collected for valid holdover.
  • Page 213 Si5345-44-42-D-RM Register 0x059D Holdover Exit BW Reg Address Bit Field Type Setting Name Description 0x059D HOLDEXIT_BW0 Set by CBPro to set the PLL bandwidth when exiting holdover, works with HOL- DEXIT_BW_SEL0 and HOLD_BW_SEL1 Register 0x059E Holdover Exit BW Reg Address Bit Field Type Setting Name...
  • Page 214 Si5345-44-42-D-RM Register 0x059A2 Holdover Exit BW Reg Address Bit Field Type Setting Name Description 0x05A2 HOLDEXIT_BW5 Set by CBPro to set the PLL bandwidth when exiting holdover, works with HOL- DEXIT_BW_SEL0 and HOLD_BW_SEL1 Register 0x05A6 Hitless Switching Control Reg Address Bit Field Type Setting Name...

  • Page 215: Registers Si5342

    Si5345-44-42-D-RM 14.5.7. Page 9 Registers Si5342 Register 0x090E XAXB Configuration Reg Address Bit Field Type Name Description 0x090E XAXB_EXTCLK_EN 0 to use a crystal at the XAXB pins 1 to use an external clock source at the XAXB pins Register 0x0943 Control I/O Voltage Select...
  • Page 216 Si5345-44-42-D-RM Register 0x094A Input Clock Enable to DSPLL Reg Address Bit Field Type Setting Name Description 0x094A INX_TO_PFD_EN Value calculated in CBPro Register 0x094E-0x094F Input Clock Buffer Hysteresis Reg Address Bit Field Type Setting Name Description 0x094E REFCLK_HYS_SEL Value calculated in CBPro 0x094F REFCLK_HYS_SEL Register 0x095E MXAXB Fractional Mode...

  • Page 217: Page A Registers Si5342

    Si5345-44-42-D-RM 14.5.8. Page A Registers Si5342 Register 0x0A02 Output Multisynth Integer Divide Mode Reg Address Bit Field Type Name Description 0x0A02 N_ADD_0P5 Value calculated in CBPro Register 0x0A03 Output Multisynth Clock to Output Driver Reg Address Bit Field Type Name...

  • Page 218: Page B Registers Si5342

    Si5345-44-42-D-RM 14.5.9. Page B Registers Si5342 Register 0x0B44 Output Multisynth Clock to Output Driver Reg Address Bit Field Type Name Description 0x0B44 PDIV_FRACN_CLK_DIS Disable digital clocks to input P (IN0–3) fractional dividers. 0x0B44 FRACN_CLK_DIS_PLL Disable digital clock to M fractional divider.

  • Page 219: Non-Standard Amplitudes

    Si5345-44-42-D-RM A—S PPENDIX ETTING THE IFFERENTIAL UTPUT RIVER TO TANDARD MPLITUDES In some applications it may be desirable to have larger or smaller differential amplitudes than produced by the standard LVPECL and LVDS settings, as selected by CBPro. In these cases, the following information describes how to implement these amplitudes by writing to the OUTx_CM and OUTx_AMPL setting names.

  • Page 220: Table 63. Typical Differential Amplitudes

    Si5345-44-42-D-RM The differential amplitude can be set as shown in Table 63. Table 63. Typical Differential Amplitudes OUTx_AMPL Normal Differential Format Low Power Differential Format (Vpp SE mV–Typical) (Vpp SE mV – Typical) 1010 1200 1350 1600 Notes: 1. In low power mode and VDDOx=1.8V, OUTx_AMPL may not be set to 6 or 7. 2.

  • Page 221: Document Change List

    Si5345-44-42-D-RM OCUMENT HANGE Revision 1.0 July 28, 2016 Initial release.  Rev. 1.0...
  • Page 222 The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death.

This manual is also suitable for:

Si5345Si5344

Table of Contents