Silicon Laboratories Si446 Series Manual
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Silicon Laboratories Si446 Series Manual

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S i44 6
API D
X
1. Introduction
This document provides API descriptions for the commands and properties used to control and configure the
Si446x family.
2. API Summary
2.1. Command Summary
Number
0x02
0x04
Number
0x00
0x01
0x10
0x11
0x12
0x13
0x14
GET_ADC_READING
0x15
0x16
0x17
0x18
0x20
0x21
0x22
0x23
0x31
0x32
0x33
REQUEST_DEVICE_STATE Request current device state.
0x34
0x36
Rev. 0.1 8/11
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
ESCRIPTIONS
Table 1. Command Summary
Boot Commands
Name
Power-up device and mode selection. Modes include operational
function.
Loads image from NVM/ROM into RAM.
Common Commands
Name
No operation command
Reports basic information about the device.
Returns the Function revision information of the device.
Sets the value of a property.
Retrieve a property's value.
Configures the GPIO pins.
Retrieve the results of possible ADC conversions.
Provides access to transmit and receive fifo counts and reset.
Returns information about the last packet received.
Calibrate Image Rejection (Si4463 and Si4464 only).
Sets the chip up for specified protocol.
Returns the interrupt status byte.
Returns the packet handler status.
Returns the modem status byte.
Returns the chip status.
Switches to TX state and starts packet transmission.
Switches to RX state. Command arguments are retained though
sleep state, so these only need to be written when they change.
Update state machine entries.
Fast RX to RX transitions for use in frequency hopping systems
Copyright © 2011 by Silicon Laboratories
AN625
Summary
Summary
AN625

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  • Page 1: Table Of Contents

    CHANGE_STATE Update state machine entries. 0x36 RX_HOP Fast RX to RX transitions for use in frequency hopping systems Rev. 0.1 8/11 Copyright © 2011 by Silicon Laboratories AN625 Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
  • Page 2 AN625 2.2. Property Summary Common Properties Number Name Default Summary 0x0100 INT_CTL_ENABLE 0x04 Interrupt enable property 0x0101 INT_CTL_PH_ENABLE 0x00 Packet handler interrupt enable property 0x0102 INT_CTL_MODEM_ENABLE 0x00 Modem interrupt enable property 0x0103 INT_CTL_CHIP_ENABLE 0x04 Chip interrupt enable property 0x0200 FRR_CTL_A_MODE 0x01 Fast Response Register A Configuration 0x0201...
  • Page 3 AN625 Common Properties Number Name Default Summary 0x1003 PREAMBLE_CONFIG_STD_2 0x0F Standard preamble configuration 0x1004 PREAMBLE_CONFIG 0x21 Preamble configuration bits 0x1005 PREAMBLE_PATTERN_31_24 Preamble pattern 0x1006 PREAMBLE_PATTERN_23_16 Preamble pattern 0x1007 PREAMBLE_PATTERN_15_8 Preamble pattern 0x1008 PREAMBLE_PATTERN_7_0 Preamble pattern 0x1100 SYNC_CONFIG 0x01 Sync configuration bits 0x1103 SYNC_BITS_15_8 0x2D...
  • Page 4 AN625 Common Properties Number Name Default Summary 0x121B PKT_FIELD_4_CONFIG 0x00 Field 4 configuration bits. 0x121C PKT_FIELD_4_CRC_CONFIG 0x00 Field 4 CRC configuration bits. 0x121D PKT_FIELD_5_LENGTH_12_8 0x00 Byte 1 of field length 0x121E PKT_FIELD_5_LENGTH_7_0 0x00 Byte 0 of field length 0x121F PKT_FIELD_5_CONFIG 0x00 Field 5 configuration bits.
  • Page 5 AN625 Common Properties Number Name Default Summary 0x2005 MODEM_DATA_RATE_0 0x40 Byte 0 of TX data rate in bps (bits per second). 0x200A MODEM_FREQ_DEV_2 0x00 Byte 2 of TX frequency deviation (a 17-bit unsigned number). This only programs the MSB of TX frequency deviation. 0x200B MODEM_FREQ_DEV_1 0x06...
  • Page 6 AN625 Common Properties Number Name Default Summary 0x300B MATCH_CTRL_4 0x00 Match 4 configuration. 0x4006 FREQ_CONTROL_W_SIZE 0x20 30 MHz clock cycles 0x4007 FREQ_CONTROL_VCOCNT_RX_ADJ 0xFF VCO target count adjustment for RX 0x5000 RX_HOP_CONTROL 0x04 RX hop control. 0x5001 RX_HOP_TABLE_SIZE 0x01 Number of entries in the RX hop table. 0x5002 RX_HOP_TABLE_ENTRY_0 No.1 entry in RX hopping table.

  • Page 7: Power_Up

    AN625 3. Commands 3.1. Boot Commands 3.1.1. POWER_UP  Summary: Power-up device and mode selection. Modes include operational function  Purpose: Power-up the device with the specified function. Power-up is complete when the CTS bit is set. This command may take ...

  • Page 8: Patch_Image

    AN625 3.1.2. PATCH_IMAGE  Summary: Loads image from NVM/ROM into RAM.  Purpose: Loads the selected function into RAM for execution or patching   Command Stream PATCH_IMAGE Command 0x04 FLAGS 0000 FUNC[3:0]  Reply Stream PATCH_IMAGE Reply CMD_COMPLETE CMD_COMPLETE[7:0] ...

  • Page 9: Nop

    AN625 3.2. Common Commands 3.2.1. NOP  Summary: No operation command  Purpose: Can be used to ensure communication with the device.   Command Stream NOP Command 0x00  Reply Stream NOP Reply CMD_COMPLETE CMD_COMPLETE[7:0]  Parameters: None  ...
  • Page 10 AN625 3.2.2. PART_INFO  Summary: Reports basic information about the device.  Purpose: Returns Part Number, Part Version, ROM ID, etc   Command Stream PART_INFO Command 0x01  Reply Stream PART_INFO Reply CMD_COMPLETE CMD_COMPLETE[7:0] CHIPREV CHIPREV[7:0] PART PART[15:8] PART PART[7:0] PBUILD PBUILD[7:0]...

  • Page 11: Part_Info

    AN625 3.2.3. FUNC_INFO  Summary: Returns the Function revision information of the device.  Purpose: Return Function revision numbers for currently loaded functional mode firmware. Contrast with PART_INFO   Command Stream FUNC_INFO Command 0x10  Reply Stream FUNC_INFO Reply CMD_COMPLETE CTS[7:0] REVEXT...

  • Page 12: Set_Property

    AN625 3.2.4. SET_PROPERTY  Summary: Sets the value of a property.  Purpose: Sets a property common to one or more commands. These are similar to parameters for a api command but are not  expected to change frequently and may be controlled by higher layers of the user's software. Setting some properties may not cause the device to take immediate action, however the property will take affect once a command which uses it is issued.
  • Page 13 AN625 DATA5[7:0] - Value of the property START_PROP + 5 (don't care if NUM_PROPS < 6 )  DATA6[7:0] - Value of the property START_PROP + 6 (don't care if NUM_PROPS < 7 )  DATA7[7:0] - Value of the property START_PROP + 7 (don't care if NUM_PROPS < 8 ) ...

  • Page 14: Get_Property

    AN625 3.2.5. GET_PROPERTY  Summary: Retrieve a property's value.  Purpose: Retrieve a property's value; The value will either be the default or the value set with SET_PROPERTY.   Command Stream GET_PROPERTY Command 0x12 GROUP GROUP[7:0] NUM_PROPS NUM_PROPS[7:0] START_PROP START_PROP[7:0] ...
  • Page 15 AN625  Response: DATA0[7:0] - Value of the property START_PROP  DATA1[7:0] - Value of the property START_PROP + 1 (don't care if NUM_PROPS < 2 )  DATA2[7:0] - Value of the property START_PROP + 2 (don't care if NUM_PROPS < 3 ) ...

  • Page 16: Gpio_Pin_Cfg

    AN625 3.2.6. GPIO_PIN_CFG  Summary: Configures the gpio pins  Command Stream GPIO_PIN_CFG Command 0x13 GPIO0 GPIO0_PULL_CTL GPIO0_MODE[5:0] GPIO1 GPIO1_PULL_CTL GPIO1_MODE[5:0] GPIO2 GPIO2_PULL_CTL GPIO2_MODE[5:0] GPIO3 GPIO3_PULL_CTL GPIO3_MODE[5:0] NIRQ NIRQ_DRV_PULL NIRQ_MODE[5:0] SDO_PULL_CTL SDO_MODE[5:0] GEN_CONFIG DRV_STRENGTH[1:0] 00000  Reply Stream GPIO_PIN_CFG Reply CMD_COMPLETE CTS[7:0] GPIO0...
  • Page 17 AN625 11 = Serial data out. 12 = Pulses high on power on reset. 13 = Pulses high when calibration timer expires. 14 = Pulses high when wakeup timer expires. 15 = unused0 16 = TX data CLK output to be used in conjuction with TX Data pin. 17 = RX data CLK output to be used in conjuction with RX Data pin.
  • Page 18 AN625 21 = RX raw data. 22 = Antenna 1 Switch used for antenna diversity. 23 = Antenna 2 Switch used for antenna diversity. 24 = High when a valid preamble is detected. Cleared when sync is received. 25 = High when an invalid preamble is detected. TODO: What clears this 26 = High when a sync word is detected.
  • Page 19 AN625 35 = High while the tx fifo is almost empty. 36 = High while the battery voltage is low. 37 = High when RSSI above clear channel assesment threshold, goes low on sync detect or exiting rx state. 38 = Toggles when hop occurs. 39 = Toggles when the hop table wraps.
  • Page 20 AN625 1 = Input and output drivers disabled. 2 = CMOS output driven low. 3 = CMOS output driven high. 4 = CMOS input. 7 = Divided MCU clock. 8 = High when command complete, low otherwise. 11 = Serial data out. 12 = Pulses high on power on reset.
  • Page 21 AN625 DRV_STRENGTH[6:5]  0 = GPIOs configured as outputs will have highest drive strength. 1 = GPIOs configured as outputs will have medium drive strength. 2 = GPIOs configured as outputs will have medium drive strength. 3 = GPIOs configured as outputs will have lowest drive strength. ...
  • Page 22 AN625 0 = Do not modify the behavior of this pin. 1 = Input and output drivers disabled. 2 = CMOS output driven low. 3 = CMOS output driven high. 4 = CMOS input. 5 = 32 kHz clock. 6 = 30 MHz clock. 7 = Divided MCU clock.
  • Page 23 AN625 10 = High when command overlap occurs. TODO: What clears this. 11 = Serial data out. 12 = Pulses high on power on reset. 13 = Pulses high when calibration timer expires. 14 = Pulses high when wakeup timer expires. 15 = unused0 16 = TX data CLK output to be used in conjuction with TX Data pin.
  • Page 24 AN625 20 = RX data. 21 = RX raw data. 22 = Antenna 1 Switch used for antenna diversity. 23 = Antenna 2 Switch used for antenna diversity. 24 = High when a valid preamble is detected. Cleared when sync is received. 25 = High when an invalid preamble is detected.
  • Page 25 AN625 3 = CMOS output driven high. 4 = CMOS input. 5 = 32 kHz clock. 7 = Divided MCU clock. 8 = High when command complete, low otherwise. 11 = Serial data out. 12 = Pulses high on power on reset. 14 = Pulses high when wakeup timer expires.
  • Page 26 AN625 3.2.7. GET_ADC_READING  Summary: Retrieve the results of possible ADC conversions.  Purpose: Retrieve the result of the last ADC conversion.   Command Stream GET_ADC_READING Command 0x14 ADC_EN TEMPERATURE_EN BATTERY_VOLTAGE_ ADC_GPIO_ ADC_GPIO_PIN[1:0]  Reply Stream GET_ADC_READING Reply CMD_COMPLETE CTS[7:0] GPIO_ADC GPIO_ADC[15:8]...

  • Page 27: Fifo_Info

    AN625 3.2.8. FIFO_INFO Summary: Provides access to transmit and receive fifo counts and reset.  Purpose:  This command is normally used for error recovery, fifo hardware does not need to be reset prior to use.  Command Stream: FIFO_INFO Command 0x15 FIFO 000000...

  • Page 28: Ircal

    AN625 3.2.10. IRCAL  Summary: Calibrate receiver image rejection for Si4463 and Si4464.  Purpose: Automatically calibrates the receiver image rejection with no requirement for an external signal source.   Command Stream IRCAL Command 0x17 SEARCHING_ INITIAL_ FINE_STEP_ COURSE_STEP_SIZE[3:0] STEP_SIZE PH_AMP SIZE[1:0]...

  • Page 29: Protocol_Cfg

    AN625 0 = Set to nominal gain 1 = Harmonics at N x 30 MHz RF_SOURCE_PWR[5:4] - Power of internal generator(Default 3).  0 = smallest 1 = small 2 = big 3 = biggest CLOSE_SHUNT_SWITCH - Close shunt switch. ...

  • Page 30: Get_Int_Status

    AN625 3.2.12. GET_INT_STATUS  Summary: Returns the interrupt status byte.  Purpose: Returns the current interrupt status byte.   Command Stream GET_INT_ STATUS Command 0x20 PH_CLR_ FILTER_ FILTER PACKET_SENT_ PACKET_ CRC32_ TX_FIFO_ RX_FIFO_ PEND MATCH_ _MISS_ PEND_CLR ERROR ALMOST_ ALMOST_ PEND_ PEND_...
  • Page 31 AN625 CHIP_PEND FIFO_ STATE_ CMD_ CHIP_ LOW_BATT_ WUT_ UNDERFLOW_ CHANGE_ ERROR_ READY_ PEND PEND OVERFLOW_ PEND PEND PEND ERROR_PEND CHIP_ FIFO_ STATE_ CMD_ CHIP_ LOW_BATT STATUS UNDERFLOW_ CHANGE ERROR READY OVERFLOW_ ERROR  Parameters FILTER_MATCH_PEND_CLR - If clear, Clear pending FILTER_MATCH interrupt. If set, leave interrupt pending ...
  • Page 32 AN625 TX_FIFO_ALMOST_EMPTY - If set, TX fifo is below watermark  RX_FIFO_ALMOST_FULL - If set, RX fifo is above watermark  INVALID_SYNC_PEND - If set, INVALID_SYNC interrupt is pending.  RSSI_JUMP_PEND - If set, RSSI_JUMP interrupt is pending.  RSSI_PEND - If set, RSSI interrupt is pending. ...

  • Page 33: Get_Ph_Status

    AN625 3.2.13. GET_PH_STATUS  Summary: Returns the packet handler status.  Purpose: Returns current packet handler status bytes and possibly clears pending packet handler interrupts.   Command Stream GET_PH_STATUS Command 0x21  Reply Stream GET_PH_ STATUS Reply CMD_ CTS[7:0] COMPLETE PH_PEND FILTER_...

  • Page 34: Get_Modem_Status

    AN625 3.2.14. GET_MODEM_STATUS  Summary: Returns the modem status byte.  Purpose: Returns and possibly clears the current modem status byte.   Command Stream GET_MODEM_STATUS Command 0x22  Reply Stream GET_MODEM_S TATUS Reply CMD_ CTS[7:0] COMPLETE MODEM_PEND INVALID_ RSSI_ RSSI_ INVALID_ PREAMBLE_...

  • Page 35: Get_Chip_Status

    AN625 3.2.15. GET_CHIP_STATUS  Summary: Returns the chip status.  Purpose: Returns current chip status bytes and possibly clears pending chip status interrupts.   Command Stream GET_CHIP_STATUS Command 0x23  Reply Stream GET_CHIP_ STATUS Reply CMD_COMP CTS[7:0] LETE CHIP_PEND FIFO_UNDERFLOW_ STATE_ CMD_...

  • Page 36: Start_Tx

    AN625 3.2.16. START_TX  Summary: Switches to TX state and starts packet transmission.  Purpose: Switches to TX state when condition is met. Command arguments are retained though sleep state, so they only need to  be written when they change. CTS will not return high until in TX state. ...

  • Page 37: Start_Rx

    AN625 3.2.17. START_RX  Summary: Switches to RX state. Command arguments are retained though sleep state, so these only need to be written when they change.  Purpose Switches to RX state when condition is met and switch to specified state when RX packet completes. Command ...
  • Page 38 AN625 RXVALID_STATE[3:0] - RX transitions to RXVALID_STATE if CRC check passes when CRC is enabled via PKT group  properties. If CRC is not enabled, upon receiving packet received interrupt, RX transitions to RXVALID_STATE. 0 = No change 1 = Sleep state. 2 = Spi Active state.
  • Page 39 AN625 3.2.18. REQUEST_DEVICE_STATE  Summary: Request current device state.  Purpose: Requests the current state of the device and lists pending TX and RX requests.   Command Stream REQUEST_DEVICE_STATE Command 0x33  Reply Stream REQUEST_DEVICE_STATE Reply CMD_COMPLETE CTS[7:0] CURR_STATE XXXX MAIN_STATE[3:0] CURRENT_CHANNEL...

  • Page 40: Change_State

    AN625 3.2.19. CHANGE_STATE  Summary: Update state machine entries.  Purpose: This command is used to manually switch to a specified state, or to cancel pending state transitions.   Command Stream CHANGE_STATE Command 0x34  Reply Stream CHANGE_STATE Reply CMD_COMPLETE CTS[7:0] ...

  • Page 41: Rx_Hop

    AN625 3.2.20. RX_HOP  Summary: Fast RX hopping  Purpose:RX Hop is designed to provide the fastest RX to RX switching time for frequency hopping systems. The RX to RX time is 75usec using this command. The VCO_CNT must be calculated offline and stored in the host.

  • Page 42: Int_Ctl_Enable

    AN625 3.3. Debug Commands 3.4. Properties 3.5. Common Properties 3.5.1. INT_CTL_ENABLE  Summary: Interrupt enable property  Purpose: Enables top-level interrupt sources   Property: 0x0100  Default: 0x04  Fields: CHIP_INT_STATUS_EN - default:1 If set, Enables CHIP_INT_STATUS interrupt.  MODEM_INT_STATUS_EN - default:0 If set, Enables MODEM_INT_STATUS interrupt.
  • Page 43 AN625 3.5.3. INT_CTL_MODEM_ENABLE  Summary: Modem interrupt enable property  Purpose: Enables modem interrupt sources   Property: 0x0102  Default: 0x00  Fields: INVALID_SYNC_EN - default:0 If set, Enables INVALID_SYNC interrupt.  RSSI_JUMP_EN - default:0 If set, Enables RSSI_JUMP interrupt. ...

  • Page 44: Frr_Ctl_A_Mode

    AN625 3.5.5. FRR_CTL_A_MODE  Summary: Fast Response Register A Configuration  Purpose: Set the data that is present in fast response register A.   Property: 0x0200  Default: 0x01  Fields: FRR_A_MODE[7:0] - default:0x01  0 = Disabled. Will always read back 0 1 = Global status 2 = Global interrupt pending 3 = Packet Handler status...

  • Page 45: Frr_Ctl_B_Mode

    AN625 3.5.6. FRR_CTL_B_MODE  Summary: Fast Response Register B Configuration  Purpose: Set the data that is present in fast response register B.   Property: 0x0201  Default: 0x02  Fields: FRR_B_MODE[7:0] - default:0x02  0 = Disabled. Will always read back 0 1 = Global status 2 = Global interrupt pending 3 = Packet Handler status...

  • Page 46: Frr_Ctl_C_Mode

    AN625 3.5.7. FRR_CTL_C_MODE  Summary: Fast Response Register C Configuration  Purpose: Set the data that is present in fast response register C.   Property: 0x0202  Default: 0x09  Fields: FRR_C_MODE[7:0] - default:0x09  0 = Disabled. Will always read back 0 1 = Global status 2 = Global interrupt pending 3 = Packet Handler status...

  • Page 47: Frr_Ctl_D_Mode

    AN625 3.5.8. FRR_CTL_D_MODE  Summary: Fast Response Register D Configuration  Purpose: Set the data that is present in fast response register D.   Property: 0x0203  Default: 0x00  Fields: FRR_A_MODE[7:0] - default:0x00  0 = Disabled. Will always read back 0 1 = Global status 2 = Global interrupt pending 3 = Packet Handler status...
  • Page 48 AN625 3.5.9. SYNC_BITS_31_24  Summary: Byte 3 of sync word  Purpose: Sync bytes are always sent bit 0 first.   Property: 0x1101  Default: 0x2D  Fields: BITS_31_24[7:0] - default:0x2D Sync bytes are always sent bit 0 first. ...

  • Page 49: Ezconfig_Modulation

    AN625 3.5.11. EZCONFIG_MODULATION  Summary: Configure modulation using the EZ config feature.  Purpose: This property selects a modulation type, modulation source and tx direct mode control if supported.   Property: 0x2400  Default: 0x02  Fields: TX_DIRECT_MODE_TYPE - default:0 ...

  • Page 50: Freq_Control_Inte

    AN625 3.5.12. FREQ_CONTROL_INTE  Summary: Frac-N PLL integer number.  Purpose: Fractional-N PLL integer number defined by the modem calculator. See datasheet for frequency equation for manual  calculation.  Property: 0x4000  Default: 0x3C  Fields: inte[6:0] - default:0x3C ...

  • Page 51: Freq_Control_Frac_1

    AN625 3.5.14. FREQ_CONTROL_FRAC_1  Summary: Byte 1 of Frac-N PLL fraction number.  Purpose: Fractional-N PLL fraction number defined by the modem calculator. See datasheet for frequency equation for manual  calculation.  Property: 0x4002  Default: 0x00  Fields: frac_1[7:0] - default:0x00 ...

  • Page 52: Freq_Control_Channel_Step_Size_1

    AN625 3.5.16. FREQ_CONTROL_CHANNEL_STEP_SIZE_1  Summary: Byte 1 of channel step size.  Purpose: Channel frequency step size used when using EZ frequency programming. EZ frequency programming is defined by base  frequency (inte + frac ) + channel number x step size. ...

  • Page 53: Global_Xo_Tune

    AN625 3.5.18. GLOBAL_XO_TUNE  Summary: Configure crystal oscillator frequency tuning bank  Purpose: Crystal oscillator frequency tuning value. 0x00 is maximum frequency value and 0x7F is lowest frequency value. Each  LSB code corresponds to a 70fF capacitance change. The total adjustment range assuming a 30MHz XTAL is +/-100ppm. ...

  • Page 54: Global_Low_Batt_Thresh

    AN625 3.5.20. GLOBAL_LOW_BATT_THRESH  Summary: Low battery threshold  Purpose: Sets the low battery threshold   Property: 0x0002  Default: 0x18  Fields: THRESHOLD[4:0] - default:0x18  Range: 0-31 - vdd_thresh = (30 + THRESH)/20. Default 2.7V 0 = 1.52 V 31 = 3.13 V ...

  • Page 55: Global_Wut_Config

    AN625 3.5.22. GLOBAL_WUT_CONFIG  Summary: GLOBAL WUT configuation  Purpose: Program WUT and enable events, Low Battery Detector support , Low Duty Cycle operation.   Property: 0x0004  Default: 0x00  Fields: WUT_LDC_EN[1:0] - default:0x0  0 = Disable LDC operation 1 = treated as wake-up - START_RX.

  • Page 56: Global_Wut_M_15_8

    AN625 3.5.23. GLOBAL_WUT_M_15_8  Summary: Configure WUT_M_15_8  Purpose: Sets HW WUT_M higher byte   Property: 0x0005  Default: 0x00  Fields: WUT_M_15_8[7:0] - default:0x00  Range: 0–255  Register View GLOBAL_WUT_M_15_8 WUT_M_15_8[7:0] 0x00 3.5.24. GLOBAL_WUT_M_7_0  Summary: Configure WUT_M_7_0 ...

  • Page 57: Global_Wut_R

    AN625 3.5.25. GLOBAL_WUT_R  Summary: Configure WUT_R  Purpose: Sets HW WUT_R   Property: 0x0007  Default: 0x00  Fields: WUT_SLEEP - default:0  0 = Go to Ready state after WUT 1 = Go to Sleep state after WUT WUT_R[4:0] - default:0x00 ...

  • Page 58: Preamble_Tx_Length

    AN625 3.5.27. PREAMBLE_TX_LENGTH  Summary: Preamble length  Purpose: Byte or nibble length of preamble to send, depends on LENGTH_CONFIG field in PREAMBLE_CONFIG property.   Property: 0x1000  Default: 0x08  Fields: TX_LENGTH[7:0] - default:0x08 Byte or nibble length of preamble to send, depends on LENGTH_CONFIG field in ...

  • Page 59: Preamble_Config_Nstd

    AN625 3.5.29. PREAMBLE_CONFIG_NSTD  Summary: Non-standard preamble configuration  Purpose: Note: This field only applies to non-standard preambles.   Property: 0x1002  Default: 0x00  Fields: RX_ERRORS[2:0] - default:0x0 Number of preamble bit errors that are allowed when detecting a valid preamble. ...

  • Page 60: Preamble_Config

    AN625 3.5.31. PREAMBLE_CONFIG  Summary: Preamble configuration bits  Purpose: Misc preamble configuration bits.   Property: 0x1004  Default: 0x21  Fields: PREAM_FIRST_1_OR_0 - default:1  0x0 = First bit is 0, calculated from the calculator. 0x1 = First bit is 1, calculated from the calculator. LENGTH_CONFIG - default:0 ...

  • Page 61: Preamble_Pattern_31_24

    AN625 3.5.32. PREAMBLE_PATTERN_31_24  Summary: Preamble pattern  Purpose: Preambles always sent bits 0-31 timewise.  Preamble pattern to be transmitted or expected to be received. Field is expressed in chips, after Manchester encoding or  before Manchester decoding. To use this register, PREAM_CONFIG_STANDARD_PREAM should be set to 0, use non-standard preamble. ...

  • Page 62: Preamble_Pattern_15_8

    AN625 3.5.34. PREAMBLE_PATTERN_15_8  Summary: Preamble pattern  Purpose: Preambles always sent bits 0-31 timewise.  Preamble pattern to be transmitted or expected to be received. Field is expressed in chips, after Manchester encoding or  before Manchester decoding. To use this register, PREAM_CONFIG_STANDARD_PREAM should be set to 0, use non-standard preamble. ...

  • Page 63: Sync_Config

    AN625 3.5.36. SYNC_CONFIG  Summary: Sync configuration bits  Purpose: Misc sync word configuration bits. Least significant bit of sync word is transmitted/received first.   Property: 0x1100  Default: 0x01  Fields: SKIP_TX - default:0  0x0 = Sync word is transmitted as defined by LENGTH field. 0x1 = Sync word is not transmitted.

  • Page 64: Sync_Bits_7_0

    AN625 3.5.38. SYNC_BITS_7_0  Summary: Byte 0 of sync word  Purpose: Sync bytes are always sent bit 0 first.   Property: 0x1104  Default: 0xD4  Fields: BITS_7_0[7:0] - default:0xD4 Sync bytes are always sent bit 0 first. ...

  • Page 65: Pkt_Config1

    AN625 3.5.40. PKT_CONFIG1  Summary: General packet configuration bits  Purpose: General packet configuration bits.   Property: 0x1206  Default: 0  Fields: PH_FIELD_SPLIT - default:0  0 = Field level properties (property 0x120D to 0x1220) are shared between TX and RX. 1 = Field level properties are split between TX and RX.

  • Page 66: Pkt_Len

    AN625 3.5.41. PKT_LEN  Summary: Provides information regarding how to use the length from the received packet.  Purpose: This property is used for variable length packet reception.   Property: 0x1208  Default: 0x00  Fields: ENDIAN - default:0 ...
  • Page 67 AN625 3.5.43. PKT_LEN_ADJUST  Summary: Adjust length field by this amount to derive the variable length information.  Purpose: This property is used to add or subtract a constant to the value extracted from the length field in the packet. ...

  • Page 68: Pkt_Rx_Threshold

    AN625 3.5.45. PKT_RX_THRESHOLD  Summary: RX almost full threshold.  Purpose: Receive almost full interrupt fires when there are RX_THRESHOLD number of bytes present in the receive fifo.   Property: 0x120C  Default: 0x30  Fields: RX_THRESHOLD[7:0] - default:0x30 Receive almost full interrupt fires when there are RX_THRESHOLD number of ...

  • Page 69: Pkt_Field_1_Length_7_0

    AN625 3.5.47. PKT_FIELD_1_LENGTH_7_0  Summary: Byte 0 of field length  Purpose: See byte 1 for details.   Property: 0x120E  Default: 0x00  Fields: FIELD_1_LENGTH_7_0[7:0] - default:0x00 See byte 1 for details.  Range: 0–0xff  Register View PKT_FIELD_1_LENGTH_7_0 FIELD_1_LENGTH_7_0[7:0] 0x00...

  • Page 70: Pkt_Field_1_Crc_Config

    AN625 3.5.49. PKT_FIELD_1_CRC_CONFIG  Summary: Field 1 CRC configuration bits.  Purpose: Field 1 CRC configuration bits.   Property: 0x1210  Default: 0x00  Fields: CRC32_START - default:0  0x1 = Load CRC engine with seed value at the start of this field using CRC32_SEED. ...

  • Page 71: Pkt_Field_2_Length_7_0

    AN625 3.5.51. PKT_FIELD_2_LENGTH_7_0  Summary: Byte 0 of field length  Purpose: See byte 1 for details.   Property: 0x1212  Default: 0x00  Fields: FIELD_2_LENGTH_7_0[7:0] - default:0x00 See byte 1 for details.  Range: 0-0xff  Register View PKT_FIELD_2_LENGTH_7_0 FIELD_2_LENGTH_7_0[7:0] 0x00...

  • Page 72: Pkt_Field_2_Crc_Config

    AN625 3.5.53. PKT_FIELD_2_CRC_CONFIG  Summary: Field 2 CRC configuration bits.  Purpose: Field 2 CRC configuration bits.   Property: 0x1214  Default: 0x00  Fields: RESERVED[1:0] - default:0x0 Reserved.  SEND_CRC32 - default:0  0x1 = Transmit CRC at the end of this field CHECK_CRC32 - default:0 ...

  • Page 73: Pkt_Field_3_Length_7_0

    AN625 3.5.55. PKT_FIELD_3_LENGTH_7_0  Summary: Byte 0 of field length  Purpose: See byte 1 for details.   Property: 0x1216  Default: 0x00  Fields: FIELD_3_LENGTH_7_0[7:0] - default:0x00 See byte 1 for details.  Range: 0–0xff  Register View PKT_FIELD_3_LENGTH_7_0 FIELD_3_LENGTH_7_0[7:0] 0x00...

  • Page 74: Pkt_Field_3_Crc_Config

    AN625 3.5.57. PKT_FIELD_3_CRC_CONFIG  Summary: Field 3 CRC configuration bits.  Purpose: Field 3 CRC configuration bits.   Property: 0x1218  Default: 0x00  Fields: RESERVED[1:0] - default:0x0 Reserved.  SEND_CRC32 - default:0  0x1 = Transmit CRC at the end of this field ...

  • Page 75: Pkt_Field_4_Length_7_0

    AN625 3.5.59. PKT_FIELD_4_LENGTH_7_0  Summary: Byte 0 of field length  Purpose: See byte 1 for details.   Property: 0x121A  Default: 0x00  Fields: FIELD_4_LENGTH_7_0[7:0] - default:0x00 See byte 1 for details.  Range: 0–0xff  Register View PKT_FIELD_4_LENGTH_7_0 FIELD_4_LENGTH_7_0[7:0] 0x00...

  • Page 76: Pkt_Field_4_Crc_Config

    AN625 3.5.61. PKT_FIELD_4_CRC_CONFIG  Summary: Field 4 CRC configuration bits.  Purpose: Field 4 CRC configuration bits.   Property: 0x121C  Default: 0x00  Fields: RESERVED[1:0] - default:0x0 Reserved.  SEND_CRC32 - default:0  0x1 = Transmit CRC at the end of this field CHECK_CRC32 - default:0 ...

  • Page 77: Pkt_Field_5_Length_7_0

    AN625 3.5.63. PKT_FIELD_5_LENGTH_7_0  Summary: Byte 0 of field length  Purpose: See byte 1 for details.   Property: 0x121E  Default: 0x00  Fields: FIELD_5_LENGTH_7_0[7:0] - default:0x00 See byte 1 for details.  Range: 0–0xff  Register View PKT_FIELD_5_LENGTH_7_0 FIELD_5_LENGTH_7_0[7:0] 0x00...

  • Page 78: Pkt_Field_5_Crc_Config

    AN625 3.5.65. PKT_FIELD_5_CRC_CONFIG  Summary: Field 5 CRC configuration bits.  Purpose: Field 5 CRC configuration bits.   Property: 0x1220  Default: 0x00  Fields: RESERVED[1:0] - default:0x0 Reserved.  SEND_CRC32 - default:0  0x1 = Transmit CRC at the end of this field CHECK_CRC32 - default:0 ...

  • Page 79: Pkt_Rx_Field_1_Length_7_0

    AN625 3.5.67. PKT_RX_FIELD_1_LENGTH_7_0  Summary: Byte 0 of field length for RX  Purpose: See byte 1 for details.   Property: 0x1222  Default: 0x00  Fields: RX_FIELD_1_LENGTH_7_0[7:0] - default:0x00 See byte 1 for details.  Range: 0–0xff  Register View PKT_RX_FIELD_1_LENGTH_7_0 RX_FIELD_1_LENGTH_7_0[7:0]...

  • Page 80: Pkt_Rx_Field_1_Crc_Config

    AN625 3.5.69. PKT_RX_FIELD_1_CRC_CONFIG  Summary: Field 1 CRC configuration bits for RX.  Purpose: Field 1 CRC configuration bits.   Property: 0x1224  Default: 0x00  Fields: CRC32_START - default:0  0x1 = Load CRC engine with seed value at the start of this field using CRC_SEED. CHECK_CRC32 - default:0 ...

  • Page 81: Pkt_Rx_Field_2_Length_7_0

    AN625 3.5.71. PKT_RX_FIELD_2_LENGTH_7_0  Summary: Byte 0 of field length for RX  Purpose: See byte 1 for details.   Property: 0x1226  Default: 0x00  Fields: RX_FIELD_2_LENGTH_7_0[7:0] - default:0x00 See byte 1 for details.  Range: 0–0xff  Register View PKT_RX_FIELD_2_LENGTH_7_0 RX_FIELD_2_LENGTH_7_0[7:0]...

  • Page 82: Pkt_Rx_Field_2_Crc_Config

    AN625 3.5.73. PKT_RX_FIELD_2_CRC_CONFIG  Summary: Field 2 CRC configuration bits for RX.  Purpose: Field 2 CRC configuration bits.   Property: 0x1228  Default: 0x00  Fields: RESERVED[1:0] - default:0x0 Reserved.  CHECK_CRC32 - default:0  0x1 = Check CRC at the end of this field CRC32_ENABLE - default:0 ...

  • Page 83: Pkt_Rx_Field_3_Length_7_0

    AN625 3.5.75. PKT_RX_FIELD_3_LENGTH_7_0  Summary: Byte 0 of field length for RX  Purpose: See byte 1 for details.   Property: 0x122A  Default: 0x00  Fields: RX_FIELD_3_LENGTH_7_0[7:0] - default:0x00 See byte 1 for details.  Range: 0–0xff  Register View PKT_RX_FIELD_3_LENGTH_7_0 RX_FIELD_3_LENGTH_7_0[7:0]...

  • Page 84: Pkt_Rx_Field_3_Crc_Config

    AN625 3.5.77. PKT_RX_FIELD_3_CRC_CONFIG  Summary: Field 3 CRC configuration bits for RX.  Purpose: Field 3 CRC configuration bits.   Property: 0x122C  Default: 0x00  Fields: RESERVED[1:0] - default:0x0 Reserved.  CHECK_CRC32 - default:0  0x1 = Check CRC at the end of this field CRC32_ENABLE - default:0 ...

  • Page 85: Pkt_Rx_Field_4_Length_7_0

    AN625 3.5.79. PKT_RX_FIELD_4_LENGTH_7_0  Summary: Byte 0 of field length for RX  Purpose: See byte 1 for details.   Property: 0x122E  Default: 0x00  Fields: RX_FIELD_4_LENGTH_7_0[7:0] - default:0x00 See byte 1 for details.  Range: 0-0xff  Register View PKT_RX_FIELD_4_LENGTH_7_0 RX_FIELD_4_LENGTH_7_0[7:0]...

  • Page 86: Pkt_Rx_Field_4_Crc_Config

    AN625 3.5.81. PKT_RX_FIELD_4_CRC_CONFIG  Summary: Field 4 CRC configuration bits for RX.  Purpose: Field 4 CRC configuration bits.   Property: 0x1230  Default: 0x00  Fields: RESERVED[1:0] - default:0x0 Reserved.  CHECK_CRC32 - default:0  0x1 = Check CRC at the end of this field CRC32_ENABLE - default:0 ...

  • Page 87: Pkt_Rx_Field_5_Length_7_0

    AN625 3.5.83. PKT_RX_FIELD_5_LENGTH_7_0  Summary: Byte 0 of field length for RX  Purpose: See byte 1 for details.   Property: 0x1232  Default: 0x00  Fields: RX_FIELD_5_LENGTH_7_0[7:0] - default:0x00 See byte 1 for details.  Range: 0–0xff  Register View PKT_RX_FIELD_5_LENGTH_7_0 RX_FIELD_5_LENGTH_7_0[7:0]...

  • Page 88: Pkt_Rx_Field_5_Crc_Config

    AN625 3.5.85. PKT_RX_FIELD_5_CRC_CONFIG  Summary: Field 5 CRC configuration bits for RX.  Purpose: Field 5 CRC configuration bits.   Property: 0x1234  Default: 0x00  Fields: RESERVED[1:0] - default:0x0 Reserved.  CHECK_CRC32 - default:0  Check CRC at the end of this field ...

  • Page 89: Modem_Mod_Type

    AN625 3.5.86. MODEM_MOD_TYPE  Summary: Modulation Type  Purpose: This property selects between OOK, FSK, 4FSK and GFSK modulation, modulation source, and tx direct mode control.  The modulator must be configured for one mode through the entire packet. If portions of the packet alternate between ...
  • Page 90 AN625 3.5.87. MODEM_MAP_CONTROL  Summary: Controls bit mapping.  Purpose: Modem Mapping Control.   Property: 0x2001  Default: 0x80  Fields: enmanch - default:1  0 = Disable Manchester coding. 1 = Enable Manchester coding. eninv_rxbit - default:0  0 = Do not invert RX data bits.

  • Page 91: Modem_Dsm_Ctrl

    AN625 3.5.88. MODEM_DSM_CTRL  Summary: DSM control  Purpose: Delta Sigma Modulator control   Property: 0x2002  Default: 0x07  Fields: dsmclk_sel - default:0 DSM clock source selection.  0 = DSM clock comes from 30MHz PLL feedback clock. 1 = DSM clock comes from 30MHz crystal clock.

  • Page 92: Modem_Data_Rate_2

    AN625 3.5.89. MODEM_DATA_RATE_2  Summary: Byte 2 of TX data rate in bps (bits per second).  Purpose: Data rate, unsigned 24-bit, 100 kbps by default.   Property: 0x2003  Default: 0x0F  Fields: dr_23_16[7:0] - default:0x0F  Range: 0–255 ...

  • Page 93: Modem_Data_Rate_0

    AN625 3.5.91. MODEM_DATA_RATE_0  Summary: Byte 0 of TX data rate in bps (bits per second).  Purpose: Data rate, unsigned 24-bit, 100 kbps by default.   Property: 0x2005  Default: 0x40  Fields: dr_7_0[7:0] - default:0x40  Range: 0–255 ...

  • Page 94: Modem_Freq_Dev_1

    AN625 3.5.93. MODEM_FREQ_DEV_1  Summary: Byte 1 of frequency deviation.  Purpose: Frequency deviation, unsigned 17-bit.   Property: 0x200B  Default: 0x06  Fields: freqdev_15_8[7:0] - default:0x06  Range: 0–255  Register View MODEM_FREQ_DEV_1 freqdev_15_8[7:0] 0x06 3.5.94. MODEM_FREQ_DEV_0  Summary: Byte 0 of frequency deviation.
  • Page 95 AN625 3.5.95. MODEM_RESERVED_20_0D  Summary:  Purpose:   Property: 0x200D  Default: 0x00  Fields: RESERVED_20_0D[7:0] - default:0x00   Register View MODEM_RESERVED_20_0D RESERVED_20_0D[7:0] 0x00 3.5.96. MODEM_RESERVED_20_0E  Summary:  Purpose:   Property: 0x200E  Default: 0x00  Fields: RESERVED_20_0E[7:0] - default:0x00 ...

  • Page 96: Modem_Ant_Div_Control

    AN625 3.5.97. MODEM_ANT_DIV_CONTROL  Summary: Specifies antenna diversity controls. Antenna diversity mode is valid for standard packet only.  Purpose: Specifies pm detection threshold and GPIO config in antenna diversity mode.   Property: 0x2049  Default: 0x80  Fields: ant2pm_thd[3:0] - default:0x8 The second phase preamble detection threshold in ANT-DIV mode.

  • Page 97: Modem_Rssi_Thresh

    AN625 3.5.98. MODEM_RSSI_THRESH  Summary: RSSI threshold control  Purpose: Selects threshold for clear channel assessment. If RSSI value is above this threshold, the CCA GPIO will be high and the  RSSI interrupt will be generated.  Property: 0x204A ...

  • Page 98: Modem_Rssi_Control

    AN625 3.5.100. MODEM_RSSI_CONTROL  Summary: RSSI control  Purpose: Selects where in the packet to latch the RSSI value in the RSSI Latch fast response register. The latched  value can also be read using GET_MODEM_STATUS command.  Property: 0x204C ...
  • Page 99 AN625 3.5.102. MODEM_RSSI_COMP  Summary: RSSI reading offset.  Purpose: Offsets RSSI curve in 1dB steps. 32 is no offset, lower will adjust RSSI down, and higher will adjust RSSI up.   Property: 0x204E  Default: 0x32  Fields: ...

  • Page 100: Pa_Mode

    AN625 3.5.104. PA_MODE  Summary: PA operating mode and groups.  Purpose: Specify PA mode and HPA/MPA groups   Property: 0x2200  Default: 0x10  Fields: PA_GROUP[3:0] - default:0x4 ODEV group and unit configuration.  0 = No groups on. 1 = Reserved 2 = Set for Si4464/63/62 3 = Reserved...

  • Page 101: Pa_Bias_Clkduty

    AN625 3.5.106. PA_BIAS_CLKDUTY  Summary: PA Bias and TX clock duty cycle configuration  Property: 0x2202  Default: 0x00  Fields: CLK_DUTY[1:0] - default:0x0 Select 25% or 50% duty cycle clocks for transmitter to improve transmit efficiency.  0 = TXP: 50%, TXN: 50% 1 = TXP: 25%, TXN: 25% 2 = TXP: 50%, TXN: 0 3 = TXP: 25%, TXN: 0...

  • Page 102: Match_Value_1

    AN625 3.5.108. MATCH_VALUE_1  Summary: Match 1 value.  Purpose:   Property: 0x3000  Default: 0x00  Fields: VALUE_1[7:0] - default:0x00  Range: 0–0xFF  Register View MATCH_VALUE_1 VALUE_1[7:0] 0x00 3.5.109. MATCH_MASK_1  Summary: Match 1 mask.  Purpose: ...

  • Page 103: Match_Ctrl_1

    AN625 3.5.110. MATCH_CTRL_1  Summary: Pacekt match enable and match 1 configuration.  Purpose: Enable packet match processing and pattern 1 matches or not.   Property: 0x3002  Default: 0x00  Fields: POLARITY - default:0  0x00 = True if packet matches. 0x01 = True if packet doesn't match.

  • Page 104: Match_Mask_2

    AN625 3.5.112. MATCH_MASK_2  Summary: Match 2 mask.  Purpose:   Property: 0x3004  Default: 0x00  Fields: MASK_2[7:0] - default:0x00  Range: 0–0xFF  Register View MATCH_MASK_2 MASK_2[7:0] 0x00 3.5.113. MATCH_CTRL_2  Summary: Match 2 configuration.  Purpose: Enable pattern 2 matches or not.

  • Page 105: Match_Value_3

    AN625 3.5.114. MATCH_VALUE_3  Summary: Match 3 value.  Purpose:   Property: 0x3006  Default: 0x00  Fields: VALUE_3[7:0] - default:0x00  Range: 0–0xFF  Register View MATCH_VALUE_3 VALUE_3[7:0] 0x00 3.5.115. MATCH_MASK_3  Summary: Match 3 mask.  Purpose: ...

  • Page 106: Match_Ctrl_3

    AN625 3.5.116. MATCH_CTRL_3  Summary: Match 3 configuration.  Purpose: Enable pattern 3 matches or not.   Property: 0x3008  Default: 0x00  Fields: POLARITY - default:0  0x00 = True if packet matches. 0x01 = True if packet doesn't match. LOGIC - default:0 ...

  • Page 107: Match_Mask_4

    AN625 3.5.118. MATCH_MASK_4  Summary: Match 4 mask.  Purpose:   Property: 0x300A  Default: 0x00  Fields: MASK_4[7:0] - default:0x00  Range: 0–0xFF  Register View MATCH_MASK_4 MASK_4[7:0] 0x00 3.5.119. MATCH_CTRL_4  Summary: Match 4 configuration.  Purpose: Enable pattern 4 matches or not.
  • Page 108 AN625 3.5.120. FREQ_CONTROL_W_SIZE  Summary: 30 MHz clock cycles  Purpose: 30 MHz clock cycles   Property: 0x4006  Default: 0x20  Fields: w_size[7:0] - default:0x20  Range: 0–255  Register View FREQ_CONTROL_W_SIZE W_SIZE[7:0] 0x20 3.5.121. FREQ_CONTROL_VCOCNT_RX_ADJ  Summary: VCO target count adjustment for RX ...
  • Page 109 AN625 3.5.122. RX_HOP_CONTROL  Summary: RX hop control.  Purpose: Sets RSSI timeout value and select RX hop condition.   Property: 0x5000  Default: 0x04  Fields: HOP_EN[2:0] - default:0x0 RX hop condition.  0 = Hop disabled 1 = Hop if preamble timeout occurs. If no preamble detected after RX preamble timeout, then hop. Otherwise a preamble is detected, stay on channel.
  • Page 110 AN625 3.5.124. RX_HOP_TABLE_ENTRY_0  Summary: No.1 entry in RX hopping table.  Purpose: No.1 entry in RX hopping table. Skip this entry if 0xFF.   Property: 0x5002  Default: 0  Fields: CHANNEL_NUM[7:0] - default:0x00  Range: 0–255 255 = Hopping entry is invalid. ...
  • Page 111 AN625 OTES Rev. 0.1...
  • Page 112 Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur.

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