Table of Contents
Advertisement
Quick Links
32-bit ARM Cortex-M3 CPU
-
50 MHz maximum frequency
Single-cycle multiplication, hardware division support
-
Nested vectored interrupt control (NVIC) with 8 priority levels
-
Memory
32–256 kB flash, in-system programmable
-
8–32 kB SRAM with configurable low power retention
-
Clock Sources
Internal oscillator with PLL: 23–50 MHz
-
-
Low power internal oscillator: 20 MHz
Low frequency internal oscillator (LFO): 16.4 kHz
-
External real-time clock (RTC) crystal oscillator
-
-
External oscillator: Crystal, RC, C, CMOS clock
Power Management
-
Three adjustable low drop-out (LDO) regulators
Power-on reset circuit and brownout detectors
-
-
DC-DC buck converter allows dynamic voltage scaling for
maximum efficiency (250 mW output)
Multiple power modes supported for low power optimization
-
Low Power Features
75 nA typical current in Power Mode 8
-
Low-current RTC (180 nA from LFO, 300 nA from crystal)
-
4 μs wakeup, register state retention and no reset required from
-
lowest power mode
175 μA/MHz at 3.6 V executing from flash
-
140 μA/MHz at 3.6 V executing from SRAM
-
Specialized on-chip charge pump reduces power consumption
-
-
Process/Voltage/Temperature (PVT) Monitor
5 V Tolerant Flexible I/O
-
Up to 62 contiguous 5 V tolerant GPIO with one priority cross-
bar providing flexibility in pin assignments
Temperature Range: –40 to +85 °C
Supply Voltage: 1.8 to 3.8 V
Rev 1.1 11/14
High-Performance, Low-Power, 32-Bit Precision32™
Analog Peripherals
-
12-Bit Analog-to-Digital Converter: Up to 250 ksps 12-bit mode
or 1 Msps 10-bit mode
10-Bit Current-mode Digital-to-Analog Converter
-
2 x Low-current comparators
-
Digital and Communication Peripherals
1 x USART with IrDA and ISO7816 Smartcard support
-
1 x UART that operates in low power mode
-
2 x SPIs, 1 x I2C, 16/32-bit CRC
-
128/192/256-bit Hardware AES Encryption
-
Encoder/Decoder: Manchester and Three-out-of-Six
-
Integrated LCD Controller: up to 160 segments (40x4), auto-
-
contrast and low power operation
Timers/Counters
3 x 32-bit or 6 x 16-bit timers with capture/compare
-
-
16-bit, 6-channel counter with capture/compare/PWM and
dead-time controller with differential outputs
16-bit low power timer/advanced capture counter operational in
-
the lowest power mode
32-bit real time clock (RTC) with multiple alarms
-
Watchdog timer
-
-
Low power mode advanced capture counter (ACCTR)
Data Transfer Peripherals
10-Channel DMA Controller
-
3 Channel Data Transfer Manager manages complex DMA
-
transfers without core intervention
On-Chip Debugging
Serial wire debug (SWD) with serial wire viewer (SWV) or JTAG
-
(no boundary scan) allow debug and programming
-
Cortex-M3 embedded trace macrocell (ETM)
Package Options
-
QFN options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm)
TQFP options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm)
-
Copyright © 2013 by Silicon Laboratories
SiM3L1xx
MCU Family with up to 256 kB of Flash
SiM3L1xx
Advertisement
Table of Contents
Related Manuals for Silicon Laboratories SiM3L1xx
Summary of Contents for Silicon Laboratories SiM3L1xx
- Page 1 QFN options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm) Temperature Range: –40 to +85 °C TQFP options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm) Supply Voltage: 1.8 to 3.8 V Rev 1.1 11/14 Copyright © 2013 by Silicon Laboratories SiM3L1xx...
- Page 2 Rev 1.1...
-
Page 3: Table Of Contents
3. Electrical Specifications......................8 3.1. Electrical Characteristics ....................8 3.2. Thermal Conditions ......................30 3.3. Absolute Maximum Ratings..................31 4. Precision32™ SiM3L1xx System Overview..............32 4.1. Power ...........................34 4.1.1. DC-DC Buck Converter (DCDC0)................34 4.1.2. Three Low Dropout LDO Regulators (LDO0) ............35 4.1.3. Voltage Supply Monitor (VMON0) ...............35 4.1.4. - Page 4 Si M3 L1 xx 4.7.2. UART (UART0)....................48 4.7.3. SPI (SPI0, SPI1) ....................49 4.7.4. I2C (I2C0) ......................49 4.8. Analog ..........................50 4.8.1. 12-Bit Analog-to-Digital Converter (SARADC0)...........50 4.8.2. 10-Bit Digital-to-Analog Converter (IDAC0) ............50 4.8.3. Low Current Comparators (CMP0, CMP1) ............50 4.9. Reset Sources......................51 4.10.Security ........................52 4.11.On-Chip Debugging .....................52 5.
-
Page 5: Related Documents And Conventions
1.1.2. Hardware Access Layer (HAL) API Description The Silicon Laboratories Hardware Access Layer (HAL) API provides C-language functions to modify and read each bit in the SiM3L1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual. 1.1.3. ARM Cortex-M3 Reference Manual The ARM-specific features like the Nested Vectored Interrupt Controller are described in the ARM Cortex-M3 reference documentation. -
Page 6: Typical Connection Diagrams
This section provides typical connection diagrams for SiM3L1xx devices. 2.1. Power Figure 2.1 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the dc-dc buck converter is not used. Figure 2.1. Connection Diagram with DC-DC Converter Unused Figure 2.2 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the internal dc-dc... - Page 7 Si M3 L 1 x x Figure 2.3. Connection Diagram with External Radio Device Figure 2.4 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the dc-dc buck converter is used and the I/O are powered separately.
-
Page 8: Electrical Specifications
Si M3 L1 xx 3. Electrical Specifications 3.1. Electrical Characteristics All electrical parameters in all Tables are specified under the conditions listed in Table 3.1, unless stated otherwise. Table 3.1. Recommended Operating Conditions Parameter Symbol Test Condition Unit Operating Supply Voltage on —... - Page 9 Si M3 L 1 x x Table 3.2. Power Consumption Parameter Symbol Test Condition Unit Digital Core Supply Current 1,2,3,4 Normal Mode —Full speed = 49 MHz, — 17.5 18.9 with code executing from flash, = 24.5 MHz peripheral clocks ON = 20 MHz, —...
- Page 10 Si M3 L1 xx Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Unit 1,2,3,4 Power Mode 1 —Full speed = 49 MHz, — 13.4 16.6 with code executing from RAM, = 24.5 MHz peripheral clocks ON = 20 MHz, —...
- Page 11 Si M3 L 1 x x Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Unit 1,2,3,4,5 Power Mode 2 —Core halted = 49 MHz, — with only Port I/O clocks on (wake = 24.5 MHz from pin). = 20 MHz, —...
- Page 12 Si M3 L1 xx Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Unit Power Mode 8 —Low Power RTC w/ 16.4 kHz LFO, — — Sleep, powered by the low power = 2.4 V, T = 25 °C mode charge pump, 32kB of reten- RTC w/ 32.768 kHz Crystal, —...
- Page 13 Si M3 L 1 x x Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Unit Advanced Capture Counter = 2.4 V, T = 25 °C, — 1.39 — nA/Hz ACCTR (ACCTR0), LC Dual or Quadrature CPMD = 01 Mode, Relative to Sampling Fre- = 3.8 V, T = 25 °C, —...
- Page 14 Si M3 L1 xx Table 3.2. Power Consumption (Continued) Parameter Symbol Test Condition Unit SARADC0 Sampling at 1 Msps, Internal — SARADC VREF used Sampling at 250 ksps, lowest — μA power mode settings. Temperature Sensor — μA TSENSE Internal SAR Reference Normal Power Mode —...
- Page 15 Si M3 L 1 x x Table 3.3. Power Mode Wake Up Times Parameter Symbol Test Condition Unit Power Mode 2 or 6 Wake Time — clocks Power Mode 3 Fast Wake Time — — μs PM3FW (using LFO as clock source) Power Mode 8 Wake Time —...
- Page 16 Si M3 L1 xx Table 3.5. On-Chip Regulators Parameter Symbol Test Condition Unit DC-DC Buck Converter Input Voltage Range — DCIN Input Supply to Output Voltage Differ- 0.45 — — DCREG ential (for regulation) Output Voltage Range 1.25 — DCOUT Output Voltage Accuracy —...
- Page 17 Si M3 L 1 x x Table 3.5. On-Chip Regulators (Continued) Parameter Symbol Test Condition Unit Memory LDO Output Setting During Programming — LDOMEM During Normal — Operation Digital LDO Output Setting < 20 MHz — LDODIG > 20 MHz —...
- Page 18 Si M3 L1 xx Table 3.6. Flash Memory Parameter Symbol Test Condition Unit Write Time One 16-bit Half Word μs WRITE Erase Time One Page ERASE Full Device ERALL Endurance (Write/Erase Cycles) 100k — Cycles Retention = 25 °C, 1k Cycles —...
- Page 19 Si M3 L 1 x x Table 3.7. Internal Oscillators Parameter Symbol Test Condition Unit Phase-Locked Loop (PLL0OSC) Calibrated Output Frequency Full Temperature and 48.3 49.7 PLL0OSC Supply Range (Free-running output mode, RANGE = 2) Power Supply Sensitivity = 25 °C, —...
- Page 20 Si M3 L1 xx Table 3.7. Internal Oscillators (Continued) Parameter Symbol Test Condition Unit RTC0 Oscillator (RTC0OSC) Missing Clock Detector Trigger — RTCMCD Frequency RTC External Input CMOS Clock — RTCEXTCLK Frequency RTC Robust Duty Cycle Range — Table 3.8. External Oscillator Parameter Symbol Test Condition...
- Page 21 Si M3 L 1 x x Table 3.9. SAR ADC Parameter Symbol Test Condition Unit Resolution 12 Bit Mode Bits bits 10 Bit Mode Bits Supply Voltage Requirements High Speed Mode — (VBAT) Low Power Mode — Throughput Rate 12 Bit Mode —...
- Page 22 Si M3 L1 xx Table 3.9. SAR ADC (Continued) Parameter Symbol Test Condition Unit Offset Temperature Coefficient — 0.004 — LSB/°C Slope Error –0.07 –0.02 0.02 Dynamic Performance (10 kHz Sine Wave Input 1dB below full scale, Max throughput) Signal-to-Noise 12 Bit Mode —...
- Page 23 Si M3 L 1 x x Table 3.10. IDAC Parameter Symbol Test Condition Unit Static Performance Resolution Bits bits Integral Nonlinearity — ±0.5 ±2 Differential Nonlinearity (Guaranteed — ±0.5 ±1 Monotonic) Output Compliance Range — — – Full Scale Output Current 2 mA Range, 1.98 2.046...
- Page 24 Si M3 L1 xx Table 3.11. ACCTR (Advanced Capture Counter) Parameter Symbol Test Condition Unit LC Comparator Response Time, +100 mV Differential — — RESP0 CMPMD = 11 –100 mV Differential — — (Highest Speed) LC Comparator Response Time, +100 mV Differential —...
- Page 25 Si M3 L 1 x x Table 3.11. ACCTR (Advanced Capture Counter) (Continued) Parameter Symbol Test Condition Unit LC Comparator Positive Hysteresis CMPHYP = 00 — 1.37 — Mode 3 (CPMD = 00) CMPHYP = 01 — — CMPHYP = 10 —...
- Page 26 Si M3 L1 xx Table 3.12. Voltage Reference Electrical Characteristics Parameter Symbol Test Condition Unit Internal Fast Settling Reference Output Voltage –40 to +85 °C, 1.65 REFFS = 1.8–3.8 V Temperature Coefficient — — ppm/°C REFFS Turn-on Time — — μs REFFS Power Supply Rejection...
- Page 27 Si M3 L 1 x x Table 3.14. Comparator Parameter Symbol Test Condition Unit Response Time, CMPMD = 00 +100 mV Differential — — RESP0 (Highest Speed) –100 mV Differential — — Response Time, CMPMD = 11 +100 mV Differential —...
- Page 28 Si M3 L1 xx Table 3.14. Comparator (Continued) Parameter Symbol Test Condition Unit Positive Hysteresis CMPHYP = 00 — 1.37 — Mode 3 (CPMD = 11) CMPHYP = 01 — — CMPHYP = 10 — — CMPHYP = 11 — 15.6 —...
- Page 29 Si M3 L 1 x x Table 3.16. Port I/O Parameter Symbol Test Condition Unit Output High Voltage (PB0, PB1, Low Drive, I = –1 mA – 0.7 — — PB3, or PB4) Low Drive, I = –10 μA – 0.1 —...
-
Page 30: Thermal Conditions
Si M3 L1 xx 3.2. Thermal Conditions Table 3.17. Thermal Conditions Parameter Symbol Test Condition Unit Thermal Resistance* — — °C/W TQFP-80 Packages — — °C/W QFN-64 Packages — — °C/W TQFP-64 Packages — — °C/W QFN-40 Packages *Note: Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad. Rev 1.1... -
Page 31: Absolute Maximum Ratings
Si M3 L 1 x x 3.3. Absolute Maximum Ratings Stresses above those listed under Table 3.18 may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. -
Page 32: Precision32™ Sim3L1Xx System Overview
On-Chip Debugging With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillators, the SiM3L1xx devices are truly stand-alone system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing non- volatile data storage and allowing field upgrades of the firmware. User firmware has complete control of all... - Page 33 Each device is specified for 1.8 to 3.8 V operation over the industrial temperature range (–40 to +85 °C). The SiM3L1xx devices are available in 40-pin or 64-pin QFN and 64-pin or 80-pin TQFP packages. All package options are lead-free and RoHS compliant. See Table 5.1 for ordering information. A block diagram is included in Figure 4.1.
-
Page 34: Power
SiM3L1xx devices also include a low power charge pump in the PMU module for use in low power modes (PM8) to further reduce the power consumption of the device. -
Page 35: Three Low Dropout Ldo Regulators (Ldo0)
4.1.4. Power Management Unit (PMU) The Power Management Unit on the SiM3L1xx manages the power systems of the device. It manages the power- up sequence during power on and the wake up sources for PM8. On power-up, the PMU ensures the core voltages are a proper value before core instruction execution begins. - Page 36 Si M3 L1 xx 4.1.5.2. Power Mode 1 and Power Mode 5 Power Mode 1 and Power Mode 5 are fully operational modes with code executing from RAM. PM5 is the same as PM1, but with the clocks operating at a lower speed. This enables power to be conserved by reducing the LDO regulator outputs.
- Page 37 4.1.5.6. Power Mode Summary The power modes described above are summarized in Table 4.1. Table 3.2 and Table 3.3 provide more information on the power consumption and wake up times for each mode. Table 4.1. SiM3L1xx Power Modes Mode Description...
-
Page 38: Process/Voltage/Temperature Monitor (Timer2 And Pvtosc0)
4.1.6. Process/Voltage/Temperature Monitor (TIMER2 and PVTOSC0) The Process/Voltage/Temperature monitor consists of two modules (TIMER2 and PVTOSC0) designed to monitor the digital circuit performance of the SiM3L1xx device. The PVT oscillator (PVTOSC0) consists of two oscillators, one operating from the memory LDO and one operating from the digital LDO. -
Page 39: I/O
Internal Pulse Generator Timer (PB0 only) to generate simple square waves and pulses. 4.2.2. Crossbar The SiM3L1xx devices have one crossbar with the following features: Flexible peripheral assignment to port pins. Pins can be individually skipped to move peripherals as needed for design or layout considerations. -
Page 40: Clocking
AHB clock divided by two. The Clock Control module on SiM3L1xx devices allows the AHB and APB clocks to be turned off to unused peripherals to save system power. Any registers in a peripheral with disabled clocks will be unable to be accessed until the clocks are enabled. -
Page 41: Pll (Pll0)
STALL bit during noise-sensitive measurements. 4.3.2. Low Power Oscillator (LPOSC0) The Low Power Oscillator is the default AHB oscillator on SiM3L1xx devices and enables or disables automatically, as needed. The default output frequency of this oscillator is factory calibrated to 20 MHz, and a divided 2.5 MHz version of this clock is also available as an AHB clock source. -
Page 42: Integrated Lcd Controller (Lcd0)
Si M3 L1 xx 4.4. Integrated LCD Controller (LCD0) SiM3L1xx devices contain an LCD segment driver and on-chip bias generation that supports static, 2-mux, 3-mux and 4-mux LCDs with 1/2 or 1/3 bias. The on-chip charge pump with programmable output voltage allows software contrast control which is independent of the supply voltage. -
Page 43: Data Peripherals
Si M3 L 1 x x 4.5. Data Peripherals 4.5.1. 10-Channel DMA Controller The DMA facilitates autonomous peripheral operation, allowing the core to finish tasks more quickly without spending time polling or waiting for peripherals to interrupt. This helps reduce the overall power consumption of the system, as the device can spend more time in low-power modes. -
Page 44: 16/32-Bit Enhanced Crc (Ecrc0)
Si M3 L1 xx 4.5.4. 16/32-bit Enhanced CRC (ECRC0) The ECRC module is designed to provide hardware calculations for flash memory verification and communications protocols. In addition to calculating a result from direct writes from firmware, the ECRC module can automatically snoop the APB bus and calculate a result from data written to or read from a particular peripheral. -
Page 45: Counters/Timers
Si M3 L 1 x x 4.6. Counters/Timers 4.6.1. 32-bit Timer (TIMER0, TIMER1, TIMER2) Each timer module is independent, and includes the following features: Operation as a single 32-bit or two independent 16-bit timers. Clocking options include the APB clock, the APB clock scaled using an 8-bit prescaler, the external ... -
Page 46: Real-Time Clock (Rtc0)
32.768 kHz watch crystal. The RTC provides three alarm events in addition to a missing clock event, which can also function as interrupt, reset, or wakeup sources on SiM3L1xx devices. The RTC module includes internal loading capacitors that are programmable to 16 discrete levels, allowing compatibility with a wide range of crystals. -
Page 47: Low Power Mode Advanced Capture Counter (Acctr0)
Supports a sample and hold mode for Wheatstone bridges. All devices in the SiM3L1xx family include the low power mode advanced capture counter (ACCTR0). Table 4.2 lists the supported inputs and outputs for each of the packages. Table 4.2. SiM3L1xx Supported Advanced Capture Counter Inputs and Outputs... -
Page 48: Communications Peripherals
Si M3 L1 xx 4.7. Communications Peripherals 4.7.1. USART (USART0) The USART uses two signals (TX and RX) to communicate serially with an external device. In addition to these signals, the USART module can optionally use a clock (UCLK) or hardware handshaking (RTS and CTS). The USART module provides the following features: Independent transmitter and receiver configurations with separate 16-bit baud rate generators. -
Page 49: Spi (Spi0, Spi1)
Si M3 L 1 x x Multiple loop-back modes supported. Multi-processor communications support. Operates at 9600, 4800, 2400, or 1200 baud in Power Mode 8. 4.7.3. SPI (SPI0, SPI1) SPI is a 3- or 4-wire communication interface that includes a clock, input data, output data, and an optional select signal. -
Page 50: Analog
Si M3 L1 xx 4.8. Analog 4.8.1. 12-Bit Analog-to-Digital Converter (SARADC0) The SARADC0 module on SiM3L1xx devices implements the Successive Approximation Register (SAR) ADC architecture. The key features of the module are as follows: Single-ended 12-bit and 10-bit modes. ... -
Page 51: Reset Sources
All RSTSRC0 registers may be locked against writes by setting the CLKRSTL bit in the LOCK0_PERIPHLOCK0 register to 1. The reset sources can also optionally reset individual modules, including the low power mode charge pump, UART0, LCD0, advanced capture counter (ACCTR0), and RTC0. Figure 4.4. SiM3L1xx Reset Sources Block Diagram Rev 1.1... -
Page 52: Security
(SWV) is available to provide a single pin to send out TPIU messages. Serial Wire Viewer is supported on all SiM3Lxxx devices. Most peripherals on SiM3L1xx devices have the option to halt or continue functioning when the core halts in debug mode. -
Page 53: Ordering Information
Serial Buses: 2 x USART, 2 x SPI, 1 x I2C Additionally, all devices in the SiM3L1xx family include the low power mode advanced capture counter (ACCTR0), though the smaller packages (SiM3L1x4) only support some of the external inputs and outputs. - Page 54 Si M3 L1 xx Table 5.1. Product Selection Guide SiM3L167-C-GQ 256 32 160 (4x40) 24 15/15 14 TQFP-80 SiM3L166-C-GM 256 32 128 (4x32) 23 14/12 11 QFN-64 SiM3L166-C-GQ 256 32 128 (4x32) 23 14/12 11 TQFP-64 ...
-
Page 55: Pin Definitions
Si M3 L 1 x x 6. Pin Definitions 6.1. SiM3L1x7 Pin Definitions Figure 6.1. SiM3L1x7-GQ Pinout Rev 1.1... - Page 56 Si M3 L1 xx Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 Pin Name Type Ground VSSDC Ground (DC- Power (I/O) VIORF Power (RF I/O) VBAT/ VBATDC VDRV VLCD Power (LCD Charge Pump) DC-DC Inductor 11 RESET Active-low Reset TCK/ JTAG / Serial SWCLK...
- Page 57 Si M3 L 1 x x Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) Pin Name Type PB0.0 Standard I/O INT0.0 ADC0.20 WAKE.0 VREF CMP0P.0 PB0.1 Standard I/O INT0.1 ADC0.21 WAKE.1 VREFGND CMP0N.0 PB0.2 Standard I/O...
- Page 58 Si M3 L1 xx Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) Pin Name Type PB0.9 Standard I/O LPT0T1 ADC0.1 INT0.9 CMP0N.1 WAKE.9 ACCTR0_LCPUL0 PB0.10 Standard I/O LPT0T2 ADC0.2 INT0.10 CMP1P.1 WAKE.10 ACCTR0_LCPUL1 PB0.11/ Standard I/O /...
- Page 59 Si M3 L 1 x x Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) Pin Name Type PB1.8 Standard I/O LCD0.31 CMP0P.3 PB1.9 Standard I/O LCD0.30 CMP0N.3 PB1.10 Standard I/O LCD0.29 CMP1P.3 PB1.11 Standard I/O ...
- Page 60 Si M3 L1 xx Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) Pin Name Type PB3.4 Standard I/O LCD0.23 INT1.12 CMP0P.6 PB3.5 Standard I/O LCD0.22 INT1.13 CMP0N.6 PB3.6 Standard I/O LCD0.21 INT1.14 CMP1P.6 PB3.7 Standard I/O...
- Page 61 Si M3 L 1 x x Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) Pin Name Type PB4.9 Standard I/O LCD0.6 PB4.10 Standard I/O LCD0.5 PB4.11/ Standard I/O / LCD0.4 ETM3 PB4.12/ Standard I/O / LCD0.3 ...
-
Page 62: Sim3L1X6 Pin Definitions
Si M3 L1 xx 6.2. SiM3L1x6 Pin Definitions Figure 6.2. SiM3L1x6-GQ Pinout Rev 1.1... - Page 63 Si M3 L 1 x x Figure 6.3. SiM3L1x6-GM Pinout Rev 1.1...
- Page 64 Si M3 L1 xx Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 Pin Name Type Ground VSSDC Ground (DC-DC) 10 Power (I/O) VIORF / Power (RF I/O) VDRV VBAT / VBATDC VLCD Power (LCD Charge Pump) DC-DC Inductor RESET Active-low Reset 57 SWCLK Serial Wire...
- Page 65 Si M3 L 1 x x Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) Pin Name Type PB0.2 Standard I/O INT0.2 ADC0.23 WAKE.3 CMP1N.0 XTAL1 PB0.3 Standard I/O INT0.3 ADC0.0 WAKE.4 CMP0P.1 IDAC0 PB0.4 Standard I/O ...
- Page 66 Si M3 L1 xx Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) Pin Name Type PB1.1 Standard I/O LCD0.30 LPT0T5 CMP0N.2 INT0.13 ACCTR0_LCBIAS1 PB1.2 Standard I/O LCD0.29 LPT0T6 CMP1P.2 INT0.14 UART0_TX PB1.3 Standard I/O LCD0.28 LPT0T7 CMP1N.2 INT0.15...
- Page 67 Si M3 L 1 x x Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) Pin Name Type PB2.5 Standard I/O VIOR LPT0T13 ADC0.8 INT1.5 CMP0N.5 SPI1_MISO PB2.6 Standard I/O VIOR LPT0T14 ADC0.9 INT1.6 CMP1P.5 SPI1_MOSI PB2.7 Standard I/O VIOR ...
- Page 68 Si M3 L1 xx Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) Pin Name Type PB4.0 Standard I/O COM0.1 PB4.1 Standard I/O COM0.0 PB4.2 Standard I/O LCD0.10 ADC0.19 PB4.3 Standard I/O LCD0.9 PB4.4 Standard I/O LCD0.8 ...
-
Page 69: Sim3L1X4 Pin Definitions
Si M3 L 1 x x 6.3. SiM3L1x4 Pin Definitions Figure 6.4. SiM3L1x4-GM Pinout Rev 1.1... - Page 70 Si M3 L1 xx Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 Pin Name Type Ground VSSDC Ground (DC-DC) Power (I/O) VIORF / Power (RF I/O) VDRV VBAT / VBATDC DC-DC Inductor RESET Active-low Reset SWCLK Serial Wire SWDIO Serial Wire RTC1 RTC Oscillator Input 34...
- Page 71 Si M3 L 1 x x Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 (Continued) Pin Name Type PB0.2 Standard I/O XBR0 INT0.2 ADC0.23 WAKE.3 CMP0N.1 CMP1N.0 XTAL1 PB0.3 Standard I/O XBR0 INT0.3 ADC0.0 WAKE.4 CMP0P.1 IDAC0 PB0.4...
- Page 72 Si M3 L1 xx Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 (Continued) Pin Name Type PB2.1 Standard I/O 28 VIORF XBR0 LPT0T9 ADC0.3 INT1.1 CMP0N.4 WAKE.13 VIORFCLK PB2.2 Standard I/O 27 VIORF XBR0 LPT0T10 ADC0.4 INT1.2 CMP1P.4 WAKE.14 PB2.3...
- Page 73 Si M3 L 1 x x Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 (Continued) Pin Name Type PB3.6 Standard I/O XBR0 INT1.14 ADC0.13 PB3.7 Standard I/O XBR0 INT1.15 ADC0.14 PB3.8 Standard I/O ADC0.15 PB3.9 Standard I/O ...
-
Page 74: Tqfp-80 Package Specifications
Si M3 L1 xx 6.4. TQFP-80 Package Specifications Figure 6.5. TQFP-80 Package Drawing Rev 1.1... - Page 75 Si M3 L 1 x x Table 6.4. TQFP-80 Package Dimensions Dimension Nominal — — 1.20 0.05 — 0.15 0.95 1.00 1.05 0.17 0.20 0.27 0.09 — 0.20 14.00 BSC 12.00 BSC 0.50 BSC 14.00 BSC 12.00 BSC 0.45 0.60 0.75 1.00 Ref ...
- Page 76 Si M3 L1 xx Figure 6.6. TQFP-80 Landing Diagram Table 6.5. TQFP-80 Landing Diagram Dimensions Dimension 13.30 13.40 13.30 13.40 0.50 BSC 0.20 0.30 1.40 1.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines. Rev 1.1...
-
Page 77: Tqfp-80 Solder Mask Design
Si M3 L 1 x x 6.4.1. TQFP-80 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm minimum, all the way around the pad. 6.4.2. -
Page 78: Qfn-64 Package Specifications
Si M3 L1 xx 6.5. QFN-64 Package Specifications Figure 6.7. QFN-64 Package Drawing Table 6.6. QFN-64 Package Dimensions Dimension Nominal 0.80 0.85 0.90 0.00 0.02 0.05 0.18 0.25 0.30 9.00 BSC 3.95 4.10 4.25 0.50 BSC 9.00 BSC 3.95 4.10 4.25 0.30 0.40... - Page 79 Si M3 L 1 x x Figure 6.8. QFN-64 Landing Diagram Table 6.7. QFN-64 Landing Diagram Dimensions Dimension 8.90 8.90 0.50 0.30 0.85 4.25 4.25 Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3.
-
Page 80: Qfn-64 Solder Mask Design
Si M3 L1 xx 6.5.1. QFN-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm minimum, all the way around the pad. 6.5.2. -
Page 81: Tqfp-64 Package Specifications
Si M3 L 1 x x 6.6. TQFP-64 Package Specifications Figure 6.9. TQFP-64 Package Drawing Rev 1.1... - Page 82 Si M3 L1 xx Table 6.8. TQFP-64 Package Dimensions Dimension Nominal — — 1.20 0.05 — 0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 — 0.20 12.00 BSC 10.00 BSC 0.50 BSC 12.00 BSC 10.00 BSC 0.45 0.60 0.75 0°...
- Page 83 Si M3 L 1 x x Figure 6.10. TQFP-64 Landing Diagram Table 6.9. TQFP-64 Landing Diagram Dimensions Dimension 11.30 11.40 11.30 11.40 0.50 BSC 0.20 0.30 1.40 1.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2.
-
Page 84: Tqfp-64 Solder Mask Design
Si M3 L1 xx 6.6.1. TQFP-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm minimum, all the way around the pad. 6.6.2. -
Page 85: Qfn-40 Package Specifications
Si M3 L 1 x x 6.7. QFN-40 Package Specifications Figure 6.11. QFN-40 Package Drawing Table 6.10. QFN-40 Package Dimensions Dimension Nominal 0.80 0.85 0.90 0.00 0.02 0.05 0.18 0.25 0.30 6.00 BSC 4.35 4.50 4.65 0.50 BSC 6.00 BSC 4.35 4.65 0.30... - Page 86 Si M3 L1 xx Figure 6.12. QFN-40 Landing Diagram Table 6.11. QFN-40 Landing Diagram Dimensions Dimension 5.90 5.90 0.50 0.30 0.85 4.65 4.65 Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3.
-
Page 87: Qfn-40 Solder Mask Design
Si M3 L 1 x x 6.7.1. QFN-40 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm minimum, all the way around the pad. 6.7.2. -
Page 88: Revision Specific Behavior
Si M3 L1 xx 7. Revision Specific Behavior This chapter describes any differences between released revisions of the device. 7.1. Revision Identification The Lot ID Code on the top side of the device package can be used for decoding device revision information. Figures 7.1, 7.2, and 7.3 show how to find the Lot ID Code on the top side of the device package. - Page 89 Si M3 L 1 x x Figure 7.3. SiM3L1x4-GM Revision Information Rev 1.1...
-
Page 90: Document Change List
Si M3 L1 xx OCUMENT HANGE Revision 0.5 to Revision 1.0 Updated Electrical Specifications Tables with latest characterization data and production test limits. Added missing signal ACCTR0_LCPUL1 to Table 6.2, “Pin Definitions and Alternate Functions for SiM3L1x6,” on page 64. Removed ACCTR0_LCIN1 and ACCTR0_STOP0/1 signals from Table 6.3, “Pin Definitions and Alternate ... -
Page 91: Contact Information
Silicon Laboratories products are not designed, intended, or authorized for use in applications intend- ed to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur.
Need help?
Do you have a question about the SiM3L1xx and is the answer not in the manual?
Questions and answers