Register Map Summary - Silicon Laboratories SI5351A/B/C Product Manual

7. Register Map Summary

The following is a summary of the register map used to read status, control, and configure the Si5351.
Register 7
0 SYS_INIT
1 SYSCAL_ LOS_B_
STKY
2 SYSCAL_ LOS_B_
MASK
3 CLK7_EN CLK6_EN
4–8
9 OEB_CLK7 OEB_CLK6
10–14
15 0
16 CLK0_PDN MS0_INT
17 CLK1_PDN MS1_INT
18 CLK2_PDN MS2_INT
19 CLK3_PDN MS3_INT
20 CLK4_PDN MS4_INT
21 CLK5_PDN MS5_INT
22 CLK6_PDN FBA_INT
23 CLK7_PDN FBB_INT
24 CLK3_DIS_STATE
25 CLK7_DIS_STATE
26–41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
6 5
LOL_B LOL_A
LOL_A_ LOS_
STKY STKY STKY
LOL_A _ LOS_
MASK MASK MASK
CLK5_EN CLK4_EN
OEB_CLK5 OEB_CLK4
0 0
MS0_SRC CLK0_INV
MS1_SRC CLK1_INV
MS2_SRC CLK2_INV
MS3_SRC CLK3_INV
MS4_SRC CLK4_INV
MS5_SRC CLK5_INV
MS6_SRC CLK6_INV
MS6_SRC CLK7_INV
CLK2_DIS_STATE
CLK6_DIS_STATE
PLL, MultiSynth, and output clock delay offset Configuration Registers.
Use ClockBuilder Desktop Software to Determine These Register Values.
R0_DIV[2:0]
MS0_P3[19:16]
R1_DIV[2:0]
MS1_P3[19:16]
R2_DIV[2:0]
MS2_P3[19:16]
Preliminary Rev. 0.95
4 3
LOS
CLK3_EN CLK2_EN
Reserved
OEB_CLK3 OEB_CLK2
Reserved
0 PLLB_SRC PLLA_SRC
CLK0_SRC[1:0]
CLK1_SRC[1:0]
CLK2_SRC[1:0]
CLK3_SRC[1:0]
CLK4_SRC[1:0]
CLK5_SRC[1:0]
CLK6_SRC[1:0]
CLK7_SRC[1:0]
CLK1_DIS_STATE
CLK5_DIS_STATE
MS0_P3[15:8]
MS0_P3[7:0]
MS0_P1[15:8]
MS0_P1[7:0]
MS0_P2[15:8]
MS0_P2[7:0]
MS1_P3[15:8]
MS1_P3[7:0]
MS1_P1[15:8]
MS1_P1[7:0]
MS1_P2[15:8]
MS1_P2[7:0]
MS2_P3[15:8]
MS2_P3[7:0]
MS2_P1[15:8]
MS2_P1[7:0]
MS2_P2[15:8]
MS2_P2[7:0]
Si5351A/B/C
2 1
REVID[1:0]
CLK1_EN CLK0_EN
OEB_CLK1 OEB_CLK0
0
CLK0_IDRV[1:0]
CLK1_IDRV[1:0]
CLK2_IDRV[1:0]
CLK3_IDRV[1:0]
CLK4_IDRV[1:0]
CLK5_IDRV[1:0]
CLK6_IDRV[1:0]
CLK7_IDRV[1:0]
CLK0_DIS_STATE
CLK4_DIS_STATE
MS0_P1[17:16]
MS0_P2[19:16]
MS1_P1[17:16]
MS1_P2[19:16]
MS2_P1[17:16]
MS2_P2[19:16]
0
0
23