Silicon Laboratories Si5397 Series Reference Manual
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Silicon Laboratories Si5397 Series Reference Manual

Silicon Laboratories Si5397 Series Reference Manual

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Si5397/96 Reference Manual
Quad/Dual DSPLL Any-frequency, Any-output Jitter
Attenuators Si5397/96 Family Reference Manual
This Family Reference Manual is intended to provide system, PCB de-
sign, signal integrity, and software engineers the necessary technical
information to successfully use the Si5397/96 devices in end applica-
tions. The official device specifications can be found in the Si5397/96
data sheets.
The Si5397 is a high-performance, jitter-attenuating clock multiplier
that integrates four any-frequency DSPLLs for applications that require
maximum integration and independent timing paths. The Si5396 is a
dual DSPLL version in a smaller package. Each DSPLL has access to
any of the four inputs and can provide low-jitter clocks on any of the
device outputs. Based on 4th generation DSPLL technology, these de-
vices provide any-frequency conversion with superior jitter perform-
ance. Each DSPLL supports independent free-run, holdover modes of
operation, and offers automatic and hitless input clock switching. The
Si5397/96 is programmable via a serial interface with in-circuit pro-
grammable non-volatile memory so that it always powers up with a
known configuration. Programming the Si5397/96 is made easy with
Silicon Labs' ClockBuilder Pro software. Factory preprogrammed devi-
ces are available.
All devices of the 9x family offer the option of an external reference or
an internal reference. Please refer to the datasheet for the different de-
vice ordering options and restrictions.
silabs.com | Building a more connected world.
RELATED DOCUMENTS
•
Si5397/96 Data Sheet
•
UG353: Si5397 Evaluation Board User's Guide
•
UG336: Si5396 Evaluation Board User's Guide
•
Recommended Crystal, TCXO, and OCXO Reference
Manual for High-Performance Jitter Attenuators and Clock
Generators
•
AN1178: Frequency-On-the-Fly for Silicon Labs Jitter
Attenuators and Clock Generators
•
AN1155: Differences between Si5342-47 and Si5392-97
Rev. 0.9

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  • Page 1 Si5397/96 Reference Manual Quad/Dual DSPLL Any-frequency, Any-output Jitter Attenuators Si5397/96 Family Reference Manual RELATED DOCUMENTS This Family Reference Manual is intended to provide system, PCB de- • Si5397/96 Data Sheet sign, signal integrity, and software engineers the necessary technical • UG353: Si5397 Evaluation Board User's Guide information to successfully use the Si5397/96 devices in end applica- •...

  • Page 2: Table Of Contents

    Table of Contents 1. Work Flow Using ClockBuilder Pro and the Register Map....6 1.1 Field Programming ......6 2.
  • Page 3 6.4.3 Programmable Common Mode Voltage for Differential Outputs ... .43 6.4.4 LVCMOS Output Terminations ..... . .43 6.4.5 LVCMOS Output Impedance and Drive Strength Selection.
  • Page 4 13.4 Grounding Vias ......88 14. Register Map ......89 14.1 Base vs.
  • Page 5 17.5 Page 4 Registers Si5396 ......292 17.6 Page 5 Registers Si5396 ......301 17.7 Page 9 Registers Si5396 .

  • Page 6: Work Flow Using Clockbuilder Pro And The Register Map

    Si5397/96 Reference Manual Work Flow Using ClockBuilder Pro and the Register Map 1. Work Flow Using ClockBuilder Pro and the Register Map This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details on how to implement them.

  • Page 7: Family Product Comparison

    Si5397/96 Reference Manual Family Product Comparison 2. Family Product Comparison The following table is a comparison of the different parts in the product family showing the differences in the inputs, MultiSynths, out- puts and package type. Table 2.1. Family Feature Comparison Internal/External Number of Multi- Part Number...

  • Page 8: Functional Description

    Si5397/96 Reference Manual Functional Description 3. Functional Description The Si5397 takes advantage of Silicon Labs fourth-generation DSPLL technology to offer the industry’s most integrated and flexible jitter attenuating clock generator solution. Each of the DSPLLs operate independently from each other and are controlled through a common serial interface.

  • Page 9: Dividers

    Si5397/96 Reference Manual Functional Description 3.1.1 Dividers There are five main divider classes within the Si5397/96. Additionally, FSTEPW can be used to adjust the nominal output frequency in DCO mode. See Section 7. Digitally-Controlled Oscillator (DCO) Mode for more information and block diagrams on DCO mode. •...

  • Page 10: Dspll Loop Bandwidth

    Si5397/96 Reference Manual Functional Description 3.1.2 DSPLL Loop Bandwidth The DSPLL loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register configurable DSPLL loop bandwidth settings in the range of 0.1 Hz to 4 kHz are available for selection. The loop bandwidth is controlled digitally and re- mains stable with less than 0.1 dB of peaking for the loop bandwidth selected.
  • Page 11 Si5397/96 Reference Manual Functional Description 3.1.2.1 Fastlock Feature Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The Fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process to reduce lock time. Higher Fastlock loop band- width settings will enable the DSPLLs to lock faster.

  • Page 12: Modes Of Operation

    Si5397/96 Reference Manual Modes of Operation 4. Modes of Operation Once initialization is complete, the DSPLL operates independently in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in the figure below. The following sections describe each of these modes in greater detail.

  • Page 13: Reset And Initialization

    Si5397/96 Reference Manual Modes of Operation 4.1 Reset and Initialization Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from internal non-volatile memory (NVM) and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete.

  • Page 14: Dynamic Pll Changes

    Si5397/96 Reference Manual Modes of Operation 4.2 Dynamic PLL Changes ClockBuilder Pro generates all necessary control register writes to update settings for the entire device, including the ones described below. This is the case for both “Export” generated files as well as when using the GUI. This is sufficient to cover most applications. However, in some applications it is desirable to modify only certain sections of the device while maintaining unaffected clocks on the remaining outputs.

  • Page 15: Nvm Programming

    Si5397/96 Reference Manual Modes of Operation 4.3 NVM Programming Devices have two categories of non-volatile memory: user NVM and Factory (Silabs) NVM. Each type is segmented into NVM banks. There are three user NVM banks, one of which is used for factory programming (whether a base part or an Orderable Part Number). User NVM can be therefore be burned in the field up to two times.

  • Page 16: Free Run Mode

    Si5397/96 Reference Manual Modes of Operation Warning: Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the NVM programming and may corrupt the register contents, as they are read from NVM. Note that this includes accesses to the PAGE register.

  • Page 17: Holdover Mode

    Si5397/96 Reference Manual Modes of Operation 4.7 Holdover Mode The DSPLL programmed for holdover mode automatically enters holdover when the selected input clock becomes invalid (i.e. when either OOF or LOS are asserted) and no other valid input clocks are available for selection. The DSPLL calculates a historical average of the input frequency while in locked mode to minimize the initial frequency offset when entering the holdover mode.
  • Page 18 Si5397/96 Reference Manual Modes of Operation Table 4.4. Holdover Mode Control Registers Setting Name Hex Address [Bit Field] Function Si5397 Si5396 Holdover Status HOLD_PLL(D,C,B,A) 000E[7:4] 000E[5:4] Holdover status indicator. Indicates when a DSPLL is in holdover or free-run mode and is not synchronized to the input reference.
  • Page 19 Si5397/96 Reference Manual Modes of Operation Setting Name Hex Address [Bit Field] Function Si5397 Si5396 HOLD_RAMP_EN_PLLA 042C[3] 042C[3] Must be set to 1 for normal operation. HOLD_RAMP_EN_PLLB 052C[3] 052C[3] HOLD_RAMP_EN_PLLC 062C[3] — HOLD_RAMP_EN_PLLD 072D[3] — silabs.com | Building a more connected world. Rev.

  • Page 20: Clock Inputs

    Si5397/96 Reference Manual Clock Inputs 5. Clock Inputs There are four inputs that can be used to synchronize any of the DSPLLs. The inputs accept both standard format inputs and low duty cycle pulsed CMOS clocks. The input P dividers can be either fractional or integer. A crosspoint between the inputs and the DSPLLs allows any of the inputs to connect to any of the DSPLLs as shown in the figure below.

  • Page 21: Manual Input Switching

    Si5397/96 Reference Manual Clock Inputs 5.1.1 Manual Input Switching In manual mode the input selection is made by writing to a register. If there is no clock signal on the selected input, the DSPLL will automatically enter holdover mode if the holdover history is valid or Freerun if it is not. Table 5.2.

  • Page 22: Types Of Inputs

    Si5397/96 Reference Manual Clock Inputs 5.2 Types of Inputs Each of the four different inputs IN0-IN3 can be configured as ac coupled differential formats such as LVDS, LVPECL, HCSL, CML, and ac-coupled single-ended CMOS formats. The standard format inputs have a nominal 50% duty cycle, must be ac-coupled and use the “Standard”...
  • Page 23 Si5397/96 Reference Manual Clock Inputs Each of the four different inputs IN0-IN3 can be configured as single ended DC-coupled standard CMOS, non-standard CMOS or pulsed CMOS inputs. In all cases, the inputs should be terminated near the device input pins. In these configurations CMOS mode is enabled via register setting "IN_PULSED_CMOS_EN"...

  • Page 24: Unused Inputs

    Si5397/96 Reference Manual Clock Inputs Non-standard CMOS refers to to a signal with a swing of (1.8V, 2.5V or 3.3 V) +/-5% that has been attenuated/level-shifted in order to comply with the specified non-standard maximum VIL and minimum VIH specifications. Please refer to the datasheet for the VIL and VIH specifications.

  • Page 25: Hitless Input Switching With Phase Buildout

    Si5397/96 Reference Manual Clock Inputs 5.2.2 Hitless Input Switching with Phase Buildout Phase buildout, also referred to as hitless switching, prevents a phase change from propagating to the output when switching between two clock inputs with an integer related frequency and a fixed phase relationship (i.e., they are phase/frequency locked, but with a non- zero phase difference).

  • Page 26: Ramped Input Switching

    Si5397/96 Reference Manual Clock Inputs 5.2.3 Ramped Input Switching When switching between input clocks that are not synchronized to the same upstream clock source (i.e. are plesiochronous) there will be differences in frequency between clocks. Ramped switching should be enabled in these cases to ensure a smooth frequency transi- tion on the outputs.

  • Page 27: Synchronizing To Gapped Input Clocks

    Si5397/96 Reference Manual Clock Inputs 5.2.6 Synchronizing to Gapped Input Clocks The DSPLL supports locking to an input clock with missing clock edges. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its edges. Gapping a clock significantly increases its jitter so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter, periodic clock.

  • Page 28: Rise Time Considerations

    Si5397/96 Reference Manual Clock Inputs 5.2.7 Rise Time Considerations It is well known that slow rise time signals with low slew rates are a cause of increased jitter. In spite of the fact that the low loop BW of the Si5397/96 will attenuate a good portion of the jitter that is associated with a slow rise time clock input, if the slew rate is low enough, the output jitter will increase.

  • Page 29: Fault Monitoring

    Si5397/96 Reference Manual Clock Inputs 5.3 Fault Monitoring All four input clocks (IN0, IN1, IN2, IN3) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown below. The refer- ence at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLLs. There is a Loss Of Lock (LOL) indicator asserted when the DSPLL loses synchronization with its reference input.

  • Page 30: Input Loss Of Signal (Los) Fault Detection

    Si5397/96 Reference Manual Clock Inputs 5.3.1 Input Loss of Signal (LOS) Fault Detection The loss of signal monitor qualifies the input signal with the following criteria to determine if a valid signal is present. The loss of signal monitor measures the period of each phase detector input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits compares the measured phase detector input period to a maximum (set) and minimum (clear) period thresholds.

  • Page 31: Out Of Frequency (Oof) Fault Detection

    Si5397/96 Reference Manual Clock Inputs Setting Name Hex Address [Bit Field] Function Si5397 Si5396 LOS(3,2,1,0)_FLG 0012[3:0] 0012[3:0] LOS status monitor sticky bits for IN3, IN2, IN1, IN0. Sticky bits will remain asserted when an LOS event oc- curs until they are cleared. Writing a zero to a sticky bit will clear it.
  • Page 32 Si5397/96 Reference Manual Clock Inputs OOF Declared Hysteresis Hysteresis OOF Cleared -4 ppm -6 ppm +4 ppm +6 ppm 0 ppm (Clear) (Set) (Clear) (Set) Reference Figure 5.10. Example of Precise OOF Monitor Assertion and De-assertion Triggers The table below lists the OOF monitoring and control registers. Because the precision OOF monitor needs to provide 1/16 ppm of fre- quency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time.

  • Page 33: Loss Of Lock (Lol) Fault Monitoring

    Si5397/96 Reference Manual Clock Inputs 5.3.3 Loss of Lock (LOL) Fault Monitoring There is a loss of lock (LOL) monitor for each of the DSPLLs. The LOL monitor asserts a LOL register bit when a DSPLL has lost synchronization with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition for each of the DSPLLs (LOL_A, LOL_B, LOL_C, LOL_D).
  • Page 34 Si5397/96 Reference Manual Clock Inputs Table 5.10. Loss of Lock Status Monitor and Control Registers Setting Name Hex Address [Bit Field] Function Si5397 Si5396 LOL Status Indicators LOL_PLL(D,C,B,A) 000E[3:0] 000E[1:0] Status bit that indicates if DSPLL A, B, C, or D is locked to an input clock.

  • Page 35: Interrupt Pin (Intr)

    Si5397/96 Reference Manual Clock Inputs 5.3.4 Interrupt Pin (INTR) An interrupt pin (INTR) indicates a change in state with any of the status indicators for any of the DSPLLs. All status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTR pin is reset by clearing the sticky status registers. Table 5.11.
  • Page 36 Si5397/96 Reference Manual Clock Inputs The _FLG bits are “sticky” versions of the alarm bits and will stay high until cleared. A _FLG bit can be cleared by writing a zero to the _FLG bit. When a _FLG bit is high and its corresponding alarm bit is low, the _FLG bit can be cleared. During run time, the source of an interrupt can be determined by reading the _FLG register values and logically ANDing them with the corresponding _MSK register bits (after inverting the _MSK bit values).

  • Page 37: Outputs

    Si5397/96 Reference Manual Outputs 6. Outputs The Si5397 supports up to eight differential output drivers and the Si5396 supports four. Each driver has a configurable voltage ampli- tude and common mode voltage covering a wide variety of differential signal formats including LVPECL, LVDS, HCSL, with CML-com- patible amplitudes.

  • Page 38: Output Crosspoint Switch

    Si5397/96 Reference Manual Outputs 6.1 Output Crosspoint Switch A crosspoint switch allows any of the output drivers to connect with any of the MultiSynths as shown in Figure 6.1 MultiSynth to Output Driver Crosspoint on page 38. The crosspoint configuration is programmable and can be stored in NVM so that the desired output configuration is ready at power up.

  • Page 39: Output Divider (R) Synchronization

    Si5397/96 Reference Manual Outputs 6.2 Output Divider (R) Synchronization All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable phase alignment. Resetting the device using the RST pin or asserting the hard reset bit 0x001E[1] will give the same result. Soft reset does not affect output alignment.

  • Page 40: Output Signal Format

    Si5397/96 Reference Manual Outputs 6.4 Output Signal Format The differential output swing and common mode voltage are both fully programmable covering a wide variety of signal formats including LVDS, LVPECL, and HCSL. For CML applications, see Section 6.4.9 Setting the Differential Output Driver to Non-Standard Amplitudes.

  • Page 41: Differential Output Terminations

    Si5397/96 Reference Manual Outputs 6.4.1 Differential Output Terminations The differential output drivers support both ac and dc-coupled terminations as shown in the following figure. DC Coupled LVDS AC Coupled CML VDD – 1.3V LVDS: V = 3.3V, 2.5V, 1.8V = 3.3V, 2.5V 0.1uF* OUTx OUTx...

  • Page 42: Differential Output Swing Modes

    Si5397/96 Reference Manual Outputs 6.4.2 Differential Output Swing Modes There are two selectable differential output swing modes: Normal and High (also called low power mode). Each output can support a unique mode. Differential Normal Swing Mode—This is the usual selection for differential outputs and should be used, unless there is a specific rea- son to do otherwise.

  • Page 43: Programmable Common Mode Voltage For Differential Outputs

    Si5397/96 Reference Manual Outputs 6.4.3 Programmable Common Mode Voltage for Differential Outputs The common mode voltage (VCM) for the differential Normal and High Swing modes is programmable in 100 mV increments from 0.7 to 2.3 V depending on the voltage available at the output's VDDO pin. Setting the common mode voltage is useful when dc coupling the output drivers.

  • Page 44: Lvcmos Output Signal Swing

    Si5397/96 Reference Manual Outputs VDDO OUTx_CMOS_DRV Source Impedance (Rs) Drive Strength (Iol/Ioh) 0x01 43 Ω 6 mA 0x02 35 Ω 8 mA 2.5 V 24 Ω 11 mA 0x03 1.8 V 31 Ω 5 mA 0x03 Note: 1. Use of the lowest impedance setting is recommended for all supply voltages. Table 6.7.

  • Page 45: Lvcmos Output Polarity

    Si5397/96 Reference Manual Outputs 6.4.7 LVCMOS Output Polarity When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on the OUTx pin is generated with the same polarity (in phase) with the clock on the OUTxb pin. The polarity of these clocks is configura- ble enabling complimentary clock generation and/or inverted polarity with respect to other output drivers.

  • Page 46: Output Driver Settings For Lvpecl, Lvds, Hcsl, And Cml

    Si5397/96 Reference Manual Outputs 6.4.8 Output Driver Settings for LVPECL, LVDS, HCSL, and CML Each differential output has four settings for control: • Normal or Low Power Format • Amplitude (sometimes called Swing) • Common Mode Voltage • Stop High or Stop Low The normal Format setting has a 100 Ω...

  • Page 47: Setting The Differential Output Driver To Non-Standard Amplitudes

    Si5397/96 Reference Manual Outputs 6.4.9 Setting the Differential Output Driver to Non-Standard Amplitudes In some applications, it may be desirable to have larger or smaller differential amplitudes than those produced by the standard LVPECL and LVDS settings, as selected by CBPro. In these cases, the following information describes how to implement these amplitudes by writing to the OUTx_CM and OUTx_AMPL setting names.

  • Page 48: Output Enable/Disable

    Si5397/96 Reference Manual Outputs Note: High-Speed Differential Mode in ClockBuilder Pro output setting page sets OUTx_AMP to 7 in order to compensate for channel loss at high frequency. See the register map portion of this document for additional information about OUTx_FORMAT, OUTx_CM and OUTx_AMPL. Contact Silicon Labs for assistance if you require a factory-programmed device to be configured for any of the output driver settings listed above.

  • Page 49: Output Driver State When Disabled

    Si5397/96 Reference Manual Outputs 6.5.1 Output Driver State When Disabled The disabled state of an output driver is configurable as disable low or disable high. When the output driver is disabled, the outputs will drive either logic high or logic low, selectable by the user. The output common mode voltage is maintained while the driver is disabled, reducing enable/disable transients.

  • Page 50: Synchronous Output Enable/Disable Feature

    Si5397/96 Reference Manual Outputs 6.5.2 Synchronous Output Enable/Disable Feature The output drivers provide a selectable synchronous enable/disable feature when OUTx_SYNC_EN = 1. Output drivers with this feature turned on will wait until a clock period has completed before the driver is disabled or enabled. This prevents unwanted runt pulses from occurring when disabling an output.

  • Page 51: Digitally-Controlled Oscillator (Dco) Mode

    Si5397/96 Reference Manual Digitally-Controlled Oscillator (DCO) Mode 7. Digitally-Controlled Oscillator (DCO) Mode The DSPLLs support a DCO mode where their output frequencies are adjustable in pre-defined steps given by frequency step words (FSTEPW). The frequency adjustments are controlled through the serial interface or by pin control using frequency increments (FINC) or decrements (FDEC).

  • Page 52: Frequency Increment/Decrement Using Pin Controls

    Si5397/96 Reference Manual Digitally-Controlled Oscillator (DCO) Mode 7.1 Frequency Increment/Decrement Using Pin Controls Controlling the output frequency with pin controls is available on the Si5397. This feature involves asserting the FINC or FDEC pins to increment or decrement the DSPLL frequency. The DSPLL_SEL pins select which DSPLL output frequency is affected by the frequen- cy change.
  • Page 53 Si5397/96 Reference Manual Digitally-Controlled Oscillator (DCO) Mode Si5397 ÷ DSPLL A Frequency Step Word 0x0423 – 0x0429 ÷ DSPLL B Frequency Step Word 0x0523 – 0x0529 ÷ DSPLL C Frequency Step Word 0x0623 – 0x0629 ÷ DSPLL D Frequency Step Word 0x0724 –...

  • Page 54: Frequency Increment/Decrement Using The Serial Interface

    Si5397/96 Reference Manual Digitally-Controlled Oscillator (DCO) Mode 7.2 Frequency Increment/Decrement Using the Serial Interface Controlling the DSPLL frequency through the serial interface is available on both the Si5397 and Si5396. This can be performed by asserting the FINC or FDEC bits to activate the frequency change defined by the frequency step word. A set of mask bits selects the DSPLL(s) that is affect by the frequency change.
  • Page 55 Si5397/96 Reference Manual Digitally-Controlled Oscillator (DCO) Mode Table 7.3. Frequency Increment/Decrement Control Registers Setting Name Hex Address [Bit Field] Function Si5397 Si5396 FINC 001D[0] 001D[0] Asserting this bit will increase the DSPLL output fre- quency by the frequency step word. FDEC 001D[1] 001D[1]...

  • Page 56: Dco With Direct Register Writes

    Si5397/96 Reference Manual Digitally-Controlled Oscillator (DCO) Mode 7.2.1 DCO with Direct Register Writes In addition to the register-based FINC/FDEC described above, updated values for the DSPLL feedback M divider value may be updated directly by the user. When the M divider numerator (Mx_NUM) and its corresponding update bit (Mx_UPDATE) is written, the new nu- merator value will take effect and the output frequency will change without any glitches.

  • Page 57: Frequency-On-The-Fly For Si5397/96

    3. Use CLI FOTF tool (create a batch script) to auto generate register files for switching among different plans. The CLI FOTF tool optimizes the VCO frequency for all of the plans “CLI User’s Guide” includes more in-depth and detailed syntax explanation and function definition. Example files are bundled in CBPro at C:\Program Files (x86)\Silicon Laboratories\ClockBuilder Pro \CLI\Samples\FOTF-For-Multi-PLL-Device.
  • Page 58 Si5397/96 Reference Manual Frequency-On-The-Fly for Si5397/96 For a more detailed information on this procedure, refer to “CBPro Tools & Support for In-System Programming” on the CBPro main page. Note that the frequency plan cannot allow an input to be shared with multiple PLLs. If an input is shared across multiple PLLs an error will be raised.

  • Page 59: Serial Interface

    Si5397/96 Reference Manual Serial Interface 9. Serial Interface Configuration and operation of the Si5397/96 is controlled by reading and writing registers using the I C or SPI serial interface. The I2C_SEL pin selects between I C or SPI operation. The Si5397/96 supports communication with either a 3.3 V or 1.8 V host by setting the IO_VDD_SEL (0x0943[0]) configuration bit.
  • Page 60 Si5397/96 Reference Manual Serial Interface Table 9.1. I C/SPI Register Settings Setting Name Hex Address [Bit Field] Function Si5397/96 IO_VDD_SEL 0x0943[0] The IO_VDD_SEL configuration bit optimizes the V and V thresholds to match the VDDS voltage. By default the IO_VDD_SEL bit is set to the VDD option. The serial interface pins are always 3.3 V tolerant even when the device's VDD pin is supplied from a 1.8 V source.

  • Page 61: I 2 C Interface

    Si5397/96 Reference Manual Serial Interface 9.1 I C Interface When in I C mode, the serial interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or Fast-Mode (400 kbps) and supports burst data transfer with auto address increments. The I C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in the figure below.
  • Page 62 Si5397/96 Reference Manual Serial Interface Read Operation – Single Byte Slv Addr [6:0] A Reg Addr [7:0] Slv Addr [6:0] Data [7:0] Read Operation - Burst (Auto Address Increment) Slv Addr [6:0] A Reg Addr [7:0] Slv Addr [6:0] Data [7:0] Data [7:0] Reg Addr +1 1 –...

  • Page 63: Spi Interface

    Si5397/96 Reference Manual Serial Interface 9.2 SPI Interface When in SPI mode, the serial interface operates in 4-wire or 3-wire depending on the state of the SPI_3WIRE configuration bit. The 4- wire interface consists of a clock input (SCLK), a chip select input (CS), serial data input (SDI), and serial data output (SDO). The 3- wire interface combines the SDI and SDO signals into a single bidirectional data pin (SDIO).
  • Page 64 Si5397/96 Reference Manual Serial Interface ‘Set Address’ and ‘Write Data’ ‘Set Addr’ Addr [7:0] ‘Write Data’ Data [7:0] ‘Set Addr’ Addr [7:0] ‘Write Data’ Data [7:0] ‘Set Addr’ Addr [7:0] ‘Write Data’ Data [7:0] ‘Set Address’ and ‘Write Data + Address Increment’ ‘Write Data + Data [7:0] ‘Set Addr’...
  • Page 65 Si5397/96 Reference Manual Serial Interface The timing diagrams for the SPI commands are shown in Figures Figure 9.9 SPI “Set Address” Command Timing on page Figure 9.10 SPI “Write Data” and “Write Data+ Address Increment” Instruction Timing on page Figure 9.11 SPI “Read Data” and “Read Data + Address Increment”...
  • Page 66 Si5397/96 Reference Manual Serial Interface Previous Next ‘Write Data’ Command Command Data byte @ base address >95 ns >95 ns Write Data instruction Data byte @ base address + 1 SCLK 4-Wire 3-Wire SDIO Don’t Care High Impedance Host Clock IC Host Clock IC Figure 9.10.
  • Page 67 Si5397/96 Reference Manual Serial Interface Previous Next ‘Read Data’ Command Command Read byte @ base address >95 ns >95 ns Read Data instruction Read byte @ base address + 1 SCLK 4-Wire 3-Wire SDIO Don’t Care High Impedance Host Clock IC Host Clock IC Figure 9.11.

  • Page 68: Xaxb References

    Si5397/96 Reference Manual XAXB References 10. XAXB References 10.1 External References An external standard low-pullability crystal (XTAL) is recommended in combination with the internal oscillator (OSC) to produce an ultra low phase noise reference clock for the DSPLL, as well as providing a stable reference for the Freerun and Holdover modes. Simplified connection diagrams are shown below.

  • Page 69: Register Settings To Configure For External Xtal Reference

    Si5397/96 Reference Manual XAXB References 10.3 Register Settings to Configure for External XTAL Reference The following registers can be used to control and make adjustments for the external reference source used. 10.3.1 XAXB_EXTCLK_EN Reference Clock Selection Register Table 10.1. XAXB External Clock Selection Register Setting Name Hex Address [Bit Field] Function...

  • Page 70: Internal Reference

    Si5397/96 Reference Manual Internal Reference 11. Internal Reference Devices with internal reference (J/K/L/M) have a 48MHz crystal integrated in the package, to deliver a smaller layout footprint and more immunity to acoustic emissions. This crystal is manufactured by a reliable Japanese crystal manufacturer and has been pre-screened for activity dips before being assembled.

  • Page 71: Crystal, Xo And Device Circuit Layout Recommendations

    Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations 12. Crystal, XO and Device Circuit Layout Recommendations The following are recommendations for crystal layout (for devices that require an external reference), as well as device layout for all variants. The main layout issues that should be carefully considered include the following: •...

  • Page 72: Si5397 Crystal Guidelines

    Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations 12.1.2 Si5397 Crystal Guidelines The following are five recommended crystal guidelines used with external reference devices: 1. Place the crystal as close as possible to the XA/XB pins. 2. DO NOT connect the crystal's GND pins to PCB gnd. 3.
  • Page 73 Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations Figure 12.2. Zoom View Crystal Shield Layer, Below the Top Layer (Layer 2) Figure 12.2 Zoom View Crystal Shield Layer, Below the Top Layer (Layer 2) on page 73 shows the layer that implements the shield underneath the crystal.
  • Page 74 Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations Figure 12.3. Crystal Ground Plane (Layer 3) silabs.com | Building a more connected world. Rev. 0.9 | 74...
  • Page 75 Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations Figure 12.4. Power Plane (Layer 4) Figure 12.5 Layer 5 Power Routing on Power Plane (Layer 5) on page 76 shows layer 5, which is the power plane with the power routed to the clock output power pins.
  • Page 76 Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations Figure 12.5. Layer 5 Power Routing on Power Plane (Layer 5) Figure 12.6 Ground Plane (Layer 6) on page 77 is another ground plane similar to layer 3. silabs.com | Building a more connected world. Rev.
  • Page 77 Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations Figure 12.6. Ground Plane (Layer 6) silabs.com | Building a more connected world. Rev. 0.9 | 77...

  • Page 78: Si5397 Output Clocks

    Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations 12.1.3 Si5397 Output Clocks Figure 12.7 Output Clock Layer (Layer 7) on page 78 shows the output clocks. Similar to the input clocks the output clocks have vias that immediately go to a buried layer with a ground plane above them and a ground flooded bottom layer. There is a ground flooding between the clock output pairs to avoid crosstalk.

  • Page 79: 64-Pin Lga Si5397 Layout Recommendations

    Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations Figure 12.8. Bottom Layer Ground Flooded (Layer 8) 12.2 64-Pin LGA Si5397 Layout Recommendations This section details the recommended guidelines for the internal reference layout. The crystal is integrated inside the package so leave XA, XB, X1, and X2 unconnected.

  • Page 80: 44-Pin Qfn Si5396 Layout Recommendations

    Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations 12.3 44-Pin QFN Si5396 Layout Recommendations This section details the layout recommendations for the 44-pin external reference devices using an example 6-layer PCB. The following guidelines details images of a six layer board with the following stack: Layer 1: device layer, with low speed CMOS control/status signals, ground flooded Layer 2: crystal shield, output clocks, ground flooded Layer 3: ground plane...

  • Page 81: Si5396 Crystal Guidelines

    Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations 12.3.2 Si5396 Crystal Guidelines The following are five recommended crystal guidelines: 1. Place the crystal as close as possible to the XA/XB pins. 2. DO NOT connect the crystal's GND pins to PCB gnd. 3.
  • Page 82 Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations Figure 12.10. Crystal Shield Layer 2 Figure 12.11 Ground Plane (Layer 3) on page 83 is the ground plane and shows a void underneath the crystal shield. silabs.com | Building a more connected world. Rev.
  • Page 83 Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations Figure 12.11. Ground Plane (Layer 3) Figure 12.12 Power Plane and Clock Output Power Supply Traces (Layer 4) on page 84 is a power plane showing the clock output power supply traces. The void underneath the crystal shield is continued. silabs.com | Building a more connected world.
  • Page 84 Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations Figure 12.12. Power Plane and Clock Output Power Supply Traces (Layer 4) Figure 12.13 Clock Input Traces (Layer 5) on page 85 shows layer 5 and the clock input traces. Similar to the clock output traces, they are routed to an inner layer and surrounded by ground to avoid crosstalk.
  • Page 85 Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations Figure 12.13. Clock Input Traces (Layer 5) Figure 12.14 Low-Speed CMOS Control and Status Signal Layer 6 (Bottom Layer) on page 86 shows the bottom layer, which contin- ues the void underneath the shield. Layer 6 and layer 1 are mainly used for low speed CMOS control and status signals for which crosstalk is not a significant issue.

  • Page 86: 44-Pin Lga Si5396 Layout Recommendations

    Si5397/96 Reference Manual Crystal, XO and Device Circuit Layout Recommendations Figure 12.14. Low-Speed CMOS Control and Status Signal Layer 6 (Bottom Layer) For any high-speed, low-jitter application, the clock signal runs should be impedance-controlled to 100 Ω differential or 50 Ω single- ended.

  • Page 87: Power Management

    Si5397/96 Reference Manual Power Management 13. Power Management 13.1 Power Management Features Several unused functions can be powered down to minimize power consumption. The registers listed below are used for powering down different features. Table 13.1. Power-Down Registers Setting Name Hex Address [Bit Field] Function Si5397A/B...

  • Page 88: Grounding Vias

    Si5397/96 Reference Manual Power Management 13.4 Grounding Vias The pad on the bottom of the device functions as both the sole electrical ground and primary heat transfer path. Hence it is important to minimize the inductance and maximize the heat transfer from this pad to the internal ground plane of the PCB. Use no fewer than 25 vias from the center pad to a ground plane under the device.

  • Page 89: Register Map

    Si5397/96 Reference Manual Register Map 14. Register Map 14.1 Base vs. Factory Preprogrammed Devices The Si5397/96 devices can be ordered as “base” or “factory-preprogrammed” (also known as “custom OPN”) versions. 14.2 “Base” Devices (a.k.a. “Blank” Devices) Example “base” orderable part numbers (OPNs) are of the form “Si5397A-E-GM” or “Si5396B-E-GM”. Base devices are available for applications where volatile reads and writes are used to program and configure the device for a particu- lar application.

  • Page 90: Register Map Overview And Default Settings Values

    Si5397/96 Reference Manual Register Map 14.4 Register Map Overview and Default Settings Values The Si5397/96 family parts have large register maps that are divided into separate “Pages” of register banks. This allows more register addresses than either the I C or SPI serial interface standards 8-bit addressing provide. Each page has a maximum of 256 addresses, however not all addresses are used on every page.

  • Page 91: Si5397A/B Register Map

    Si5397/96 Reference Manual Si5397A/B Register Map 15. Si5397A/B Register Map 15.1 Page 0 Registers Si5397A/B Table 15.1. 0x0000 Die Rev Reg Address Bit Field Type Setting Name Description 0x0000 DIE_REV 4- bit Die Revision Number Table 15.2. 0x0001 Page Reg Address Bit Field Type Setting Name...
  • Page 92 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.6. 0x0006–0x0008 TOOL_VERSION Reg Address Bit Field Type Name Description 0x0006 TOOL_VERSION[3:0] Special 0x0006 TOOL_VERSION[7:4] Revision 0x0007 TOOL_VERSION[15:8] Minor[7:0] 0x0008 TOOL_VERSION[15:8] Minor[8] 0x0008 TOOL_VERSION[16] Major 0x0008 TOOL_VERSION[13:17] Tool. 0 for ClockBuilder Pro Table 15.7. 0x0009–0x000A NVM Identifier, Pkg ID Reg Address Bit Field Type...
  • Page 93 Si5397/96 Reference Manual Si5397A/B Register Map Bit 1 is the LOS status monitor for the XTAL or REFCLK at the XA/XB pins. Bit 3 is the XAXB problem status monitor and may indicate the XAXB input signal has excessive jitter, ringing, or low amplitude. Bit 5 indicates a timeout error when using SMBUS with the I serial port.
  • Page 94 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Setting Name Description 0x0011 SMBUS_TIME- Sticky version of SMBUS_TIMEOUT. Write a 0 to this OUT_FLG bit to clear. These are sticky flag versions of 0x000C. They are cleared by writing zero to the bit that has been set. Table 15.14.
  • Page 95 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.18. 0x0017 Fault Masks Reg Address Bit Field Type Setting Name Description 0x0017 SYSIN- 1 to mask SYSINCAL_FLG from causing an interrupt CAL_INTR_MSK 0x0017 LOS- 1 to mask the LOSXAXB_FLG from causing an interrupt XAXB_INTR_MSK 0x0017 LOS-...
  • Page 96 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.21. 0x001A INCAL Masks Reg Address Bit Field Type Setting Name Description 0x001A CAL_INTR_MSK_D 1: To mask the DSPLL internal calibration busy flag SPLL[D:A] DSPLL A corresponds to bit 0 DSPLL B corresponds to bit 1 DSPLL C corresponds to bit 2 DSPLL D corresponds to bit 3 Table 15.22.
  • Page 97 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.25. 0x0020 DSPLL_SEL[1:0] Control of FINC/FDEC for DCO Reg Address Bit Field Type Name Description 0x0020 FSTEP_PLL_SIN- 0: DSPLL_SEL[1:0] pins and bits are disabled. 1: DSPLL_SEL[1:0] pins or FSTEP_PLL bits are ena- bled. See FSTEP_PLL_REGCTRL 0x0020 FSTEP_PLL_REGC Only functions when FSTEP_PLL_SINGLE = 1.
  • Page 98 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.28. 0x002D Loss of Signal Re-Qualification Value Reg Address Bit Field Type Setting Name Description 0x002D LOS0_VAL_TIME Clock Input 0 0: For 2 msec 1: For 100 msec 2: For 200 msec 3: For one second 0x002D LOS1_VAL_TIME Clock Input 1, same as above...
  • Page 99 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.33. 0x0036-0x0037 LOS0 Clear Threshold Reg Address Bit Field Type Setting Name Description 0x0036 LOS0_CLR_THR 16-bit Threshold Value 0x0037 15:8 LOS0_CLR_THR ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 0, given a particular frequency plan. Table 15.34.
  • Page 100 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.39. 0x0040 OOF Reference Select Reg Address Bit Field Type Setting Name Description 0x0040 OOF_REF_SEL 0: IN0 1: IN1 2: IN2 3: IN3 4: XAXB 5–7: Reserved ClockBuilder Pro provides the OOF register values for a particular frequency plan. Table 15.40.
  • Page 101 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.43. 0x004E-0x004F OOF Detection Windows Reg Address Bit Field Type Setting Name Description 0x004E OOF0_DET- Values calculated by CBPro. WIN_SEL 0x004E OOF1_DET- WIN_SEL 0x004F OOF2_DET- WIN_SEL 0x004F OOF3_DET- WIN_SEL Table 15.44. 0x0050 Reg Address Bit Field Type Setting Name...
  • Page 102 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.47. 0x0059 Fast OOF Detection Windows Reg Address Bit Field Type Setting Name Description 0x0059 FAST_OOF0_DET- Values calculated by CBPro. WIN_SEL 0x0059 FAST_OOF1_DET- WIN_SEL 0x0059 FAST_OOF2_DET- WIN_SEL 0x0059 FAST_OOF3_DET- WIN_SEL Table 15.48. 0x005A-0x005D OOF0 Ratio for Reference Reg Address Bit Field Type...
  • Page 103 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.52. 0x0092 Fast LOL Enable Reg Address Bit Field Type Setting Name Description 0x0092 LOL_FST_EN_PLL Enables fast detection of LOL for PLLx. A large input frequency error will quickly assert LOL when this is ena- bled.
  • Page 104 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.56. 0x0098-0x0099 Fast LOL Clear Threshold Reg Address Bit Field Type Setting Name Description 0x0098 LOL_FST_CLR_TH Values calculated by CBPro R_SEL_PLLA 0x0098 LOL_FST_CLR_TH R_SEL_PLLB 0x0099 LOL_FST_CLR_TH R_SEL_PLLC 0x0099 LOL_FST_CLR_TH R_SEL_PLLD Table 15.57. 0x009A LOL Enable Reg Address Bit Field Type...
  • Page 105 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.59. 0x009D Slow LOL Detection Value Reg Address Bit Field Type Setting Name Description 0x009D LOL_SLW_VAL- Values calculated by CBPro WIN_SEL_PLLA 0x009D LOL_SLW_VAL- WIN_SEL_PLLB 0x009D LOL_SLW_VAL- WIN_SEL_PLLC 0x009D LOL_SLW_VAL- WIN_SEL_PLLD Table 15.60. 0x009E LOL Set Thresholds Reg Address Bit Field Type...
  • Page 106 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.63. 0x00A1 LOL Clear Thresholds Reg Address Bit Field Type Setting Name Description 0x00A1 LOL_SLW_CLR_TH Configures the loss of lock clear thresholds. See list be- R_PLLC low for selectable values. 0x00A1 LOL_SLW_CLR_TH Configures the loss of lock clear thresholds. See list be- R_PLLD low for selectable values.
  • Page 107 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.66. 0x00A9-0x00AC LOL Clear Delay DSPLL B Reg Address Bit Field Type Setting Name Description 0x00A9 LOL_CLR_DE- 29-bit value. Sets the clear timer 0x00AA 15:8 R/W LAY_DIV256_PLLB LOL_CLR_DLY for LOL. CBPro sets this value. 0x00AA 15:8 LOL_CLR_DE-...
  • Page 108 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.70. 0x00E3 Reg Address Bit Field Type Setting Name Description 0x00E3 NVM_WRITE Write 0xC7 to initiate an NVM bank burn. Table 15.71. 0x00E4 Reg Address Bit Field Type Setting Name Description 0x00E4 NVM_READ_BANK When set, this bit will read the NVM down into the vola- tile memory.
  • Page 109 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.75. 0x00EE-0x00F1 FASTLOCK_EXTEND_PLLC Reg Address Bit Field Type Setting Name Description 0x00EE FASTLOCK_EX- 29-bit value. Set by CBPro to minimize the phase tran- TEND_PLLC sients when switching the PLL bandwidth. See FAST- LOCK_EXTEND_SCL_PLLx. 0x00EF 15:8 FASTLOCK_EX-...
  • Page 110 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.79. 0x00F8 Reg Address Bit Field Type Name Description 0x00F8 LOS_INTR Set by CBPro. 0x00F8 OOF_INTR Set by CBPro. Table 15.80. 0x00F9 Reg Address Bit Field Type Name Description 0x00F9 LOL_INTR_PLL[ Set by CBPro. D:A] 0x00F9 HOLD_INTR_PL...

  • Page 111: Registers Si5397A/B

    Si5397/96 Reference Manual Si5397A/B Register Map 15.2 Page 1 Registers Si5397A/B Table 15.82. 0x0102 Global OE Gating for all Clock Output Drivers Reg Address Bit Field Type Setting Name Description 0x0102 OUTALL_DISA- 0: Disables all output drivers BLE_LOW 1: Pass through the output enables. Table 15.83.
  • Page 112 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Setting Name Description 0x0108 OUT0_RDIV_FORC Force Rx output divider divide-by-2. 0x0112 0: Rx_REG sets divide value (default) OUT1_RDIV_FORC 0x0117 1: Divide value forced to divide-by-2 0x011C OUT2_RDIV_FORC 0x0126 OUT3_RDIV_FORC 0x012B 0x0130 OUT4_RDIV_FORC...
  • Page 113 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Setting Name Description 0x0109 OUT0_DIS_STATE Determines the state of an output driver when disabled, selectable as 0x0113 OUT1_DIS_STATE 0: Disable low 0x0118 OUT2_DIS_STATE 1: Disable high 0x011D OUT3_DIS_STATE 2-3: Reserved 0x0127 OUT4_DIS_STATE 0x012C...
  • Page 114 Si5397/96 Reference Manual Si5397A/B Register Map ClockBuilder Pro is used to select the correct settings for this register. The output drivers are all identical. Table 15.86. 0x010B, 0x0115, 0x011A, 0x011F, 0x0129, 0x012E, 0x0133, 0x013D Output Format Reg Address Bit Field Type Setting Name Description...
  • Page 115 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Setting Name Description 0x010B OUT0_INV LVCMOS output inversion. Only applies when OUT0A_FORMAT = 4. See for more information. 0x0115 OUT1_INV 0x011A OUT2_INV 0x011F OUT3_INV 0x0129 OUT4_INV 0x012E OUT5_INV 0x0133 OUT6_INV 0x013D OUT7_INV...
  • Page 116 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.89. 0x0141 Output Disable Mask for LOS XAXB Reg Address Bit Field Type Setting Name Description 0x0141 OUT_DIS_MSK_PL Set by CBPro 0x0141 OUT_DIS_MSK_PL 0x0141 OUT_DIS_MSK_PL 0x0141 OUT_DIS_MSK_PL 0x0141 OUT_DIS_LOL_MS 0x0141 OUT_DIS_LOS- Determines if outputs are disabled during an LOSXAXB XAXB_MSK condition.

  • Page 117: Registers Si5397A/B

    Si5397/96 Reference Manual Si5397A/B Register Map 15.3 Page 2 Registers Si5397A/B Table 15.91. 0x0206 Pre-scale Reference Divide Ratio Reg Address Bit Field Type Setting Name Description 0x0206 PXAXB The divider value for the XAXB input This valid with external clock sources, not crystals. •...
  • Page 118 Si5397/96 Reference Manual Si5397A/B Register Map Register Address Description Size Same as Address 0x0226-0x022B P3_NUM 48-bit Integer Number 0x0208-0x020D 0x022C-0x022F P3_DEN 32-bit Integer Number 0x020E-0x0211 The following set of registers configure the P-dividers corresponding to each of the four input clocks seen in . ClockBuilder Pro calcu- lates the correct values for the P-dividers.
  • Page 119 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.99. 0x0234 P3 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0234 P3_FRACN_MODE P3 (IN3) input divider fractional mode. Must be set to 0xB for proper operation. 0x0234 P3_FRAC_EN P3 (IN3) input divider fractional enable 0: Integer-only division.
  • Page 120 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.103. 0x024A-0x024C R0 Divider Reg Address Bit Field Type Setting Name Description 0x024A R0_REG 24-bit Integer output divider 0x024B 15:8 R0_REG divide value = (R0_REG+1) x 2 0x024C 23:16 R0_REG To set R0 = 2, set OUT0_RDIV_FORCE2 = 1 and then the R0_REG value is irrelevant.
  • Page 121 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.106. 0x0278-0x027C OPN Identifier Reg Address Bit Field Type Setting Name Description 0x0278 OPN_ID0 OPN unique identifier. ASCII encoded. For example, with OPN: 0x0279 15:8 OPN_ID1 5397C-A12345-GM, 12345 is the OPN unique identifier: 0x027A 23:16 OPN_ID2...
  • Page 122 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.110. 0x028E-0x0291 Reg Address Bit Field Type Setting Name Description 0x028E OOF0_CLR_THR_ The OOF0 clear threshold extension (increases thresh- old precision from 2 ppm to 0.0625 ppm) 0x028F OOF1_CLR_THR_ The OOF1 clear threshold extension (increases thresh- old precision from 2 ppm to 0.0625 ppm) 0x0290 OOF2_CLR_THR_...
  • Page 123 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.114. 0x0297 FASTLOCK_DLY_ONSW_EN_PLLx Reg Address Bit Field Type Setting Name Description 0x0297 FAST- Set by CBPro. LOCK_DLY_ONSW _EN_PLLA 0x0297 FAST- LOCK_DLY_ONSW _EN_PLLB 0x0297 FAST- LOCK_DLY_ONSW _EN_PLLC 0x0297 FAST- LOCK_DLY_ONSW _EN_PLLD Table 15.115. 0x0299 FASTLOCK_DLY_ONLOL_EN_PLLx Reg Address Bit Field Type...
  • Page 124 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.117. 0x029D-0x029F FASTLOCK_DLY_ONLOL_PLLB Reg Address Bit Field Type Setting Name Description 0x029D FAST- Set by CBPro. LOCK_DLY_ON- LOL_PLLB 0x029E 15:8 FAST- LOCK_DLY_ON- LOL_PLLB 0x029F 19:16 FAST- LOCK_DLY_ON- LOL_PLLB Table 15.118. 0x02A0-0x02A2 FASTLOCK_DLY_ONLOL_PLLC Reg Address Bit Field Type Setting Name...
  • Page 125 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.120. 0x02A6-0x02A8 FASTLOCK DLY ONSW PLLA Reg Address Bit Field Type Setting Name Description 0x02A6 FAST- 20-bit value. Set by CBPro. LOCK_DLY_ONSW _PLLA 0x02A7 15:8 FAST- LOCK_DLY_ONSW _PLLA 0x02A8 19:16 FAST- LOCK_DLY_ONSW _PLLA Table 15.121.
  • Page 126 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.123. 0x02AF-0x02B1 FASTLOCK_DLY_ONSW_PLLD Reg Address Bit Field Type Setting Name Description 0x02AF FAST- 20-bit value. Set by CBPro. LOCK_DLY_ONSW _PLLD 0x02B0 15:8 FAST- LOCK_DLY_ONSW _PLLD 0x02B1 19:16 FAST- LOCK_DLY_ONSW _PLLD Table 15.124. 0x02B7 LOL_NOSIG_TIME_PLLx Reg Address Bit Field Type...
  • Page 127 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.127. 0x02BC Reg Address Bit Field Type Setting Name Description 0x02BC LOS_CMOS_MIN_ Set by CBPro. PER_EN silabs.com | Building a more connected world. Rev. 0.9 | 127...

  • Page 128: Registers Si5397A/B

    Si5397/96 Reference Manual Si5397A/B Register Map 15.4 Page 3 Registers Si5397A/B Table 15.128. 0x0302-0x0307 N0 Numerator Reg Address Bit Field Type Setting Name Description 0x0302 N0_NUM N Output Divider Numerator. 44-bit 0x0303 15:8 Integer. 0x0304 23:16 0x0305 31:24 0x0306 39:32 0x0307 43:40 Table 15.129.
  • Page 129 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.132. 0x0338 All DSPLL Internal Dividers Update Bit Reg Address Bit Field Type Setting Name Description 0x0338 N_UPDATE Writing a 1 to this bit will update all DSPLL internal di- vider values. When this bit is written, all other bits in this register must be written as zeros.

  • Page 130: Registers Si5397A/B

    Si5397/96 Reference Manual Si5397A/B Register Map 15.5 Page 4 Registers Si5397A/B Table 15.133. 0x0407 DSPLL A Active Input Reg Address Bit Field Type Setting Name Description 0x0407 IN_PLLA_ACTV Currently selected DSPLL input clock. 0: IN0 1: IN1 2: IN2 3: IN3 Table 15.134.
  • Page 131 Si5397/96 Reference Manual Si5397A/B Register Map BWx_PLLA, FAST_BWx_PLLA, and BWx_HO_PLLA parameters to take effect. Note that individual SOFT_RST_PLLA (0x001C[1]) does not update the bandwidth parameters. Table 15.136. 0x0415-0x041B MA Divider Numerator for DSPLL A Reg Address Bit Field Type Setting Name Description 0x0415 M_NUM_PLLA...
  • Page 132 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.140. 0x0422 DSPLL A FINC/FDEC Control Reg Address Bit Field Type Setting Name Description 0x0422 M_FSTEP_MSK_P 0: To enable FINC/FDEC updates. 1: To disable FINC/FDEC updates. 0x0422 M_FSTEP_DEN_PL Set by CBPro. Table 15.141. 0x0423-0x0429 DSPLLA MA Divider Frequency Step Word Reg Address Bit Field Type...
  • Page 133 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.144. 0x042C Holdover Exit Control Reg Address Bit Field Type Setting Name Description 0x042C HOLD_EN_PLLA Holdover Enable 0: Holdover Disabled 1: Holdover Enabled 0x042C HOLD_RAMP_BYP Set by CBPro. _PLLA 0x042C HOLDEX- Holdover Exit Bandwidth select. Selects the exit band- IT_BW_SEL1_PLLA width from Holdover when ramped exit is disabled (HOLD_RAMP_BYP_PLLA = 1).
  • Page 134 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.149. 0x0432 Reg Address Bit Field Type Setting Name Description 0x0432 HOLD_15M_CYC_ Value calculated by CBPro COUNT_PLLA 0x0433 15:8 HOLD_15M_CYC_ COUNT_PLLA 0x0434 23:16 HOLD_15M_CYC_ COUNT_PLLA Table 15.150. 0x0435 DSPLL A Force Holdover Reg Address Bit Field Type Setting Name...
  • Page 135 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.153. 0x0438 DSPLL A Clock Inputs 0 and 1 Priority Reg Address Bit Field Type Setting Name Description 0x0438 IN0_PRIORI- The priority for clock input 0 is: TY_PLLA 0: No priority 1: For priority 1 2: For priority 2 3: For priority 3 4: For priority 4...
  • Page 136 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.155. 0x043A Hitless Switching Mode Reg Address Bit Field Type Setting Name Description 0x043A HSW_MODE_PLLA 1: Default setting, do not modify 0,2,3: Reserved 0x043A HSW_PHMEAS_CT 0: Default setting, do not modify RL_PLLA 1,2,3: Reserved Table 15.156.
  • Page 137 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.160. 0x0442-0x0444 Reg Address Bit Field Type Setting Name Description 0x0442 FINE_ADJ_OVR_P Set by CBPro 0x0443 15:8 FINE_ADJ_OVR_P 0x0444 17:16 FINE_ADJ_OVR_P Table 15.161. 0x0445 Reg Address Bit Field Type Setting Name Description 0x0445 FORCE_FINE_ADJ Set by CBPro _PLLA...
  • Page 138 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Setting Name Description 0x049B HOLD_FRZ_WITH_ Set by CBPro. INTONLY_PLLA 0x049B HOLDEX- Set by CBPro. IT_BW_SEL0_PLLA 0x049B HOLDEX- Set by CBPro. IT_STD_BO_PLLA Table 15.166. 0x049C Reg Address Bit Field Type Setting Name Description 0x049C...
  • Page 139 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.170. 0x04AC-0x04B2 Reg Address Bit Field Type Setting Name Description 0x04AC OUT_MAX_LIM- Set by CBPro. IT_EN_PLLA 0x04AC HOLD_SET- Set by CBPro. TLE_DET_EN_PLL 0x04AD 15:0 OUT_MAX_LIM- Set by CBPro. IT_LMT_PLLA 0x04B1 15:0 HOLD_SET- Set by CBPro. TLE_TAR- GET_PLLA silabs.com | Building a more connected world.

  • Page 140: Registers Si5397A/B

    Si5397/96 Reference Manual Si5397A/B Register Map 15.6 Page 5 Registers Si5397A/B Table 15.171. 0x0507 DSPLL B Active Input Reg Address Bit Field Type Setting Name Description 0x0507 IN_PLLB_ACTV Currently selected DSPLL input clock 0: IN0 1: IN1 2: IN2 3: IN3 Table 15.172.
  • Page 141 Si5397/96 Reference Manual Si5397A/B Register Map the BWx_PLLB, FAST_BWx_PLLB, and BWx_HO_PLLB parameters to take effect. Note that individual SOFT_RST_PLLB (0x001C[2]) does not update the bandwidth parameters. Table 15.174. 0x0515-0x051B MB Divider Numerator for DSPLL B Reg Address Bit Field Type Setting Name Description 0x0515...
  • Page 142 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.178. 0x0522 DSPLL B FINC/FDEC Control Reg Address Bit Field Type Setting Name Description 0x0522 M_FSTEP_MSK_P 0: To enable FINC/FDEC updates 1: To disable FINC/FDEC updates 0x0522 M_FSTEPW_DEN_ 0: Modify numerator PLLB 1: Modify denominator Table 15.179.
  • Page 143 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Setting Name Description 0x052B FAST- 0: For normal operation LOCK_MAN_PLLB 1: For force fast lock Table 15.182. 0x052C DSPLL B Holdover Control Reg Address Bit Field Type Setting Name Description 0x052C HOLD_EN_PLLB...
  • Page 144 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.187. 0x0532 Reg Address Bit Field Type Setting Name Description 0x0532 HOLD_15M_CYC_ Set by CBPro. COUNT_PLLB 0x0533 15:8 HOLD_15M_CYC_ COUNT_PLLB 0x0534 23:16 HOLD_15M_CYC_ COUNT_PLLB Table 15.188. 0x0535 DSPLL B Force Holdover Reg Address Bit Field Type Setting Name...
  • Page 145 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.191. 0x0538 DSPLL B Clock Inputs 0 and 1 Priority Reg Address Bit Field Type Setting Name Description 0x0538 IN0_PRIORI- The priority for clock input 0 is: TY_PLLB 0: No priority 1: For priority 1 2: For priority 2 3: For priority 3 4: For priority 4...
  • Page 146 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.193. 0x053A DSPLL B Hitless Switching Mode Reg Address Bit Field Type Setting Name Description 0x053A HSW_MODE_PLLB 1:Default setting, do not modify 0,2,3: Reserved 0x053A HSW_PHMEAS_CT 0: Default setting, do not modify RL_PLLB 1,2,3: Reserved Table 15.194.
  • Page 147 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.198. 0x0542-0x0544 FINE_ADJ_OVR_PLLB Reg Address Bit Field Type Setting Name Description 0x0542 FINE_ADJ_OVR_P Set by CBPro. 0x0543 15:8 FINE_ADJ_OVR_P 0x0544 17:16 FINE_ADJ_OVR_P Table 15.199. 0x0545 FORCE_FINE_ADJ_PLLB Reg Address Bit Field Type Setting Name Description 0x0545 FORCE_FINE_ADJ...
  • Page 148 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.203. 0x059B HOLDEXIT_BW_SEL0_PLLB Reg Address Bit Field Type Setting Name Description 0x059B Set by CBPro. IT_LP_CLOSE_HO _PLLB 0x059B HO_SKIP_PHASE_ PLLB 0x059B HOLD_PRE- SERVE_HIST_PLL 0x059B HOLD_FRZ_WITH_ INTONLY_PLLB 0x059B HOLDEX- IT_BW_SEL0_PLLB 0x059B HOLDEX- IT_STD_BO_PLLB Table 15.204. 0x059C Reg Address Bit Field Type...
  • Page 149 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.206. 0x05A4-0x05A5 Reg Address Bit Field Type Setting Name Description 0x05A4 HSW_LIMIT_PLLB Set by CBPro. 0x05A5 HSW_LIMIT_AC- Set by CBPro. TION_PLLB Table 15.207. 0x05A6 Reg Address Bit Field Type Setting Name Description 0x05A6 RAMP_STEP_SIZE Sets the size of the frequency step when frequency _PLLB...

  • Page 150: Registers Si5397A/B

    Si5397/96 Reference Manual Si5397A/B Register Map 15.7 Page 6 Registers Si5397A/B Table 15.209. 0x0607 DSPLL C Active Input Reg Address Bit Field Type Setting Name Description 0x0607 IN_PLLC_ACTV Currently selected DSPLL input clock 0: IN0 1: IN1 2: IN2 3: IN3 Table 15.210.
  • Page 151 Si5397/96 Reference Manual Si5397A/B Register Map the BWx_PLLC, FAST_BWx_PLLC, and BWx_HO_PLLC parameters to take effect. Note that individual SOFT_RST_PLLC (0x001C[3]) does not update the bandwidth parameters. Table 15.212. 0x0615-0x061B MC Divider Numerator for DSPLL C Reg Address Bit Field Type Setting Name Description 0x0615...
  • Page 152 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.216. 0x0622 DSPLL C FINC/FDEC Control Reg Address Bit Field Type Setting Name Description 0x0622 M_FSTEP_MSK_P 0: To enable FINC/FDEC updates. 1: To disable FINC/FDEC updates. 0x0622 M_FSTEPW_DEN_ 0: Modify numerator PLLC 1: Modify denominator Table 15.217.
  • Page 153 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.220. 0x062C DSPLL C Holdover Control Reg Address Bit Field Type Setting Name Description 0x062C HOLD_EN_PLLC 0: Holdover disabled 1: Holdover enabled 0x062C HOLD_RAMP_BYP Must be set to 1 for normal operation. _PLLC 0x062C HOLD_EX- 0: Use Fastlock bandwidth for Holdover Entry/Exit (de-...
  • Page 154 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.225. 0x0632-0x0634 Reg Address Bit Field Type Setting Name Description 0x0632 HOLD_15M_CYC_ Set by CBPro. COUNT_PLLC 0x0633 15:8 HOLD_15M_CYC_ COUNT_PLLC 0x0634 23:16 HOLD_15M_CYC_ COUNT_PLLC Table 15.226. 0x0635 DSPLL C Force Holdover Reg Address Bit Field Type Setting Name...
  • Page 155 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.229. 0x0638 DSPLL C Clock Inputs 0 and 1 Priority Reg Address Bit Field Type Setting Name Description 0x0638 IN0_PRIORI- The priority for clock input 0 is: TY_PLLC 0: No priority 1: For priority 1 2: For priority 2 3: For priority 3 4: For priority 4...
  • Page 156 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.231. 0x063A Hitless Switching Mode Reg Address Bit Field Type Setting Name Description 0x063A HSW_MODE_PLLC 1:Default setting, do not modify 0,2,3: Reserved 0x063A HSW_PHMEAS_CT 0: Default setting, do not modify RL_PLLC 1,2,3: Reserved Table 15.232.
  • Page 157 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.236. 0x0642-0x0644 Reg Address Bit Field Type Setting Name Description 0x0642 FINE_ADJ_OVR_P Set by CBPro. 0x0643 15:8 FINE_ADJ_OVR_P 0x0644 17:16 FINE_ADJ_OVR_P Table 15.237. 0x0645 Reg Address Bit Field Type Setting Name Description 0x0645 FORCE_FINE_ADJ Set by CBPro.
  • Page 158 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Setting Name Description 0x069B HOLD_FRZ_WITH_ Set by CBPro. INTONLY_PLLC 0x069B HOLDEX- Set by CBPro. IT_BW_SEL0_PLL 0x069B HOLDEX- Set by CBPro. IT_STD_BO_PLLC Table 15.242. 0x069C Reg Address Bit Field Type Setting Name Description 0x069C...
  • Page 159 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.245. 0x06A6 Reg Address Bit Field Type Setting Name Description 0x06A6 RAMP_STEP_SIZE Set by CBPro. _PLLC 0x06A6 RAMP_SWITCH_E N_PLLC Table 15.246. 0x06AC-0x06B2 Reg Address Bit Field Type Setting Name Description 0x06AC OUT_MAX_LIM- Set by CBPro. IT_EN_PLLC 0x06AC HOLD_SET-...

  • Page 160: Registers Si5397A/B

    Si5397/96 Reference Manual Si5397A/B Register Map 15.8 Page 7 Registers Si5397A/B Note that register addresses for Page 7 DSPLL D Registers 0x0709–0x074D are incremented relative to similar DSPLL A/B/C address- es on Pages 4, 5, and 6. For example, Register 0x0709 has the equivalent function to Registers 0x0408/0x0508/0x0608. Table 15.247.
  • Page 161 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Setting Name Description 0x0715 BW_UP- 0: No effect DATE_PLLD 1: Update both the Normal and Fastlock BWs for PLL This group of registers determines the DSPLL Fastlock bandwidth. Clock Builder Pro will then determine the values for each of these registers.
  • Page 162 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Setting Name Description 0x0722 M_FRAC_EN_PLL M feedback divider fractional enable. 0: Integer-only division 1: Fractional (or integer) division - Required for DCO operation. 0x0722 Reserved Must be set to 1 for DSPLL D Table 15.254.
  • Page 163 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.257. 0x072C DSPLL D Fast Lock Control Reg Address Bit Field Type Setting Name Description 0x072C FASTLOCK_AU- Applies when FASTLOCK_MAN_PLLD=0. TO_EN_PLLD 0: Disable Auto Fastlock 1: Enable Auto Fastlock when PLLD is out of lock 0x072C FAST- 0: For normal operation...
  • Page 164 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.262. 0x0732 Reg Address Bit Field Type Setting Name Description 0x0732 HOLD_REF_COUN 5- bit value T_FRC_PLLD Table 15.263. 0x0733-0x0735 Reg Address Bit Field Type Setting Name Description 0x0733 HOLD_15M_CYC_ Set by CBPro. COUNT_PLLD 0x0734 15:8 HOLD_15M_CYC_...
  • Page 165 Si5397/96 Reference Manual Si5397A/B Register Map For each of the four clock inputs the OOF and or the LOS alarms can be used for the clock selection logic or they can be masked from it. Note that the clock selection logic can affect entry into holdover. IN0 Input 0 applies to LOS alarm 0x0738[0], OOF alarm 0x0738[4] IN1 Input 1 applies to LOS alarm 0x0738[1], OOF alarm 0x0738[5] IN2 Input 2 applies to LOS alarm 0x0738[2], OOF alarm 0x0738[6]...
  • Page 166 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Setting Name Description 0x073A IN3_PRIORI- The priority for clock input 3 is: TY_PLLD 0: No priority 1: For priority 1 2: For priority 2 3: For priority 3 4: For priority 4 5–7: Reserved Table 15.269.
  • Page 167 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Setting Name Description 0x0740 FASTLOCK_STA- Fastlock engaged indicator. TUS_PLLD 0: DSPLL Loop BW is active 1: Fastlock DSPLL BW currently being used When the input fails or is switched and the DSPLL switches to Holdover or Freerun mode, HOLD_HIST_VALID_PLLD accumulation will stop.
  • Page 168 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Setting Name Description 0x079B HOLD_PRE- Set by CBPro. SERVE_HIST_PLL 0x079B HOLD_FRZ_WITH_ Set by CBPro. INTONLY_PLLD 0x079B HOLDEX- Set by CBPro. IT_BW_SEL0_PLL 0x079B HOLDEX- Set by CBPro. IT_STD_BO_PLLD Table 15.279. 0x079C Reg Address Bit Field Type...
  • Page 169 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.282. 0x07A6 Reg Address Bit Field Type Setting Name Description 0x07A6 RAMP_STEP_SIZE Set by CBPro. _PLLD 0x07A6 RAMP_SWITCH_E N_PLLD Table 15.283. 0x07AC-0x07B2 Reg Address Bit Field Type Setting Name Description 0x07AC OUT_MAX_LIM- Set by CBPro. IT_EN_PLLD 0x07AC HOLD_SET-...

  • Page 170: Registers Si5397A/B

    Si5397/96 Reference Manual Si5397A/B Register Map 15.9 Page 9 Registers Si5397A/B Table 15.284. 0x090E XAXB Configuration Reg Address Bit Field Type Setting Name Description 0x090E XAXB_EXTCLK_EN Selects between the XTAL or external reference clock on the XA/XB pins. Default is 0, XTAL. Set to 1 to use an external reference oscillator.

  • Page 171: Page A Registers Si5397A/B

    Si5397/96 Reference Manual Si5397A/B Register Map Table 15.289. 0x095E MXAXB Fractional Mode Reg Address Bit Field Type Setting Name Description 0x095E MXAXB_INTEGER 0: Integer MXAXB 1: Fractional MXAXB 15.10 Page A Registers Si5397A/B Table 15.290. 0x0A03 Enable DSPLL Internal Divider Clocks Reg Address Bit Field Type...

  • Page 172: Page B Registers Si5397A/B

    Si5397/96 Reference Manual Si5397A/B Register Map 15.11 Page B Registers Si5397A/B Table 15.293. 0x0B24 Reserved Control Reg Address Bit Field Type Name Description 0x0B24 RESERVED Internal use for initilization. See CBPro. Table 15.294. 0x0B25 Reserved Control Reg Address Bit Field Type Name Description...
  • Page 173 Si5397/96 Reference Manual Si5397A/B Register Map Reg Address Bit Field Type Name Description 0x0B44 FRACN_CLK_DIS_ Clock disable for the fractional divide of the M divider in PLLD PLLD. Must be set to a 0 if this M divider has a fraction- al value.
  • Page 174 Si5397/96 Reference Manual Si5397A/B Register Map ClockBuilder Pro handles these bits when changing settings for all portions of the device. This control bit is only needed when changing the settings for only a portion of the device while the remaining portion of the device operates undisturbed. Table 15.301.

  • Page 175: Page C Registers Si5397A/B

    Si5397/96 Reference Manual Si5397A/B Register Map 15.12 Page C Registers Si5397A/B Table 15.303. 0x0C02 Reg Address Bit Field Type Name Description 0x0C02 VAL_DIV_CTL0 Set by CBPro 0x0C02 VAL_DIV_CTL1 Set by CBPro Table 15.304. 0x0C03 Reg Address Bit Field Type Name Description 0x0C03 IN_CLK_VAL_PWR_UP_DIS...
  • Page 176 Si5397/96 Reference Manual Si5397A/B Register Map Table 15.311. 0x0C0B Reg Address Bit Field Type Name Description 0x0C0B IN_CLK_VAL_EN Set by CBPro _PLLD Table 15.312. 0x0C0C Reg Address Bit Field Type Name Description 0x0C0C IN_CLK_VAL_TIME_P Set by CBPro silabs.com | Building a more connected world. Rev.

  • Page 177: Si5397C/D Register Map

    Si5397/96 Reference Manual Si5397C/D Register Map 16. Si5397C/D Register Map 16.1 Page 0 Registers Si5397C/D Table 16.1. 0x0000 Die Rev Reg Address Bit Field Type Setting Name Description 0x0000 DIE_REV 4- bit Die Revision Number Table 16.2. 0x0001 Page Reg Address Bit Field Type Setting Name...
  • Page 178 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.6. 0x0006–0x0008 TOOL_VERSION Reg Address Bit Field Type Name Description 0x0006 TOOL_VERSION[3:0] Special 0x0006 TOOL_VERSION[7:4] Revision 0x0007 TOOL_VERSION[15:8] Minor[7:0] 0x0008 TOOL_VERSION[15:8] Minor[8] 0x0008 TOOL_VERSION[16] Major 0x0008 TOOL_VERSION[13:17] Tool. 0 for ClockBuilder Pro Table 16.7. 0x0009–0x000A NVM Identifier, Pkg ID Reg Address Bit Field Type...
  • Page 179 Si5397/96 Reference Manual Si5397C/D Register Map Bit 1 is the LOS status monitor for the XTAL or REFCLK at the XA/XB pins. Bit 3 is the XAXB problem status monitor and may indicate the XAXB input signal has excessive jitter, ringing, or low amplitude. Bit 5 indicates a timeout error when using SMBUS with the I serial port.
  • Page 180 Si5397/96 Reference Manual Si5397C/D Register Map Reg Address Bit Field Type Setting Name Description 0x0011 SMBUS_TIME- Sticky version of SMBUS_TIMEOUT. Write a 0 to this OUT_FLG bit to clear. These are sticky flag versions of 0x000C. They are cleared by writing zero to the bit that has been set. Table 16.14.
  • Page 181 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.18. 0x0017 Fault Masks Reg Address Bit Field Type Setting Name Description 0x0017 SYSIN- 1 to mask SYSINCAL_FLG from causing an interrupt CAL_INTR_MSK 0x0017 LOS- 1 to mask the LOSXAXB_FLG from causing an interrupt XAXB_INTR_MSK 0x0017 LOS-...
  • Page 182 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.21. 0x001A INCAL Masks Reg Address Bit Field Type Setting Name Description 0x001A CAL_INTR_MSK_D 1: To mask the DSPLL internal calibration busy flag SPLL[D:A] DSPLL A corresponds to bit 0 DSPLL B corresponds to bit 1 DSPLL C corresponds to bit 2 DSPLL D corresponds to bit 3 Table 16.22.
  • Page 183 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.25. 0x0020 DSPLL_SEL[1:0] Control of FINC/FDEC for DCO Reg Address Bit Field Type Name Description 0x0020 FSTEP_PLL_SIN- 0: DSPLL_SEL[1:0] pins and bits are disabled. 1: DSPLL_SEL[1:0] pins or FSTEP_PLL bits are ena- bled. See FSTEP_PLL_REGCTRL 0x0020 FSTEP_PLL_REGC Only functions when FSTEP_PLL_SINGLE = 1.
  • Page 184 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.28. 0x002D Loss of Signal Re-Qualification Value Reg Address Bit Field Type Setting Name Description 0x002D LOS0_VAL_TIME Clock Input 0 0: For 2 msec 1: For 100 msec 2: For 200 msec 3: For one second 0x002D LOS1_VAL_TIME Clock Input 1, same as above...
  • Page 185 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.33. 0x0036-0x0037 LOS0 Clear Threshold Reg Address Bit Field Type Setting Name Description 0x0036 LOS0_CLR_THR 16-bit Threshold Value 0x0037 15:8 LOS0_CLR_THR ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 0, given a particular frequency plan. Table 16.34.
  • Page 186 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.39. 0x0040 OOF Reference Select Reg Address Bit Field Type Setting Name Description 0x0040 OOF_REF_SEL 0: IN0 1: IN1 2: IN2 3: IN3 4: XAXB 5–7: Reserved ClockBuilder Pro provides the OOF register values for a particular frequency plan. Table 16.40.
  • Page 187 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.43. 0x004E-0x004F OOF Detection Windows Reg Address Bit Field Type Setting Name Description 0x004E OOF0_DET- Values calculated by CBPro. WIN_SEL 0x004E OOF1_DET- WIN_SEL 0x004F OOF2_DET- WIN_SEL 0x004F OOF3_DET- WIN_SEL Table 16.44. 0x0050 Reg Address Bit Field Type Setting Name...
  • Page 188 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.47. 0x0059 Fast OOF Detection Windows Reg Address Bit Field Type Setting Name Description 0x0059 FAST_OOF0_DET- Values calculated by CBPro. WIN_SEL 0x0059 FAST_OOF1_DET- WIN_SEL 0x0059 FAST_OOF2_DET- WIN_SEL 0x0059 FAST_OOF3_DET- WIN_SEL Table 16.48. 0x005A-0x005D OOF0 Ratio for Reference Reg Address Bit Field Type...
  • Page 189 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.52. 0x0092 Fast LOL Enable Reg Address Bit Field Type Setting Name Description 0x0092 LOL_FST_EN_PLL Enables fast detection of LOL for PLLx. A large input frequency error will quickly assert LOL when this is ena- bled.
  • Page 190 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.56. 0x0098-0x0099 Fast LOL Clear Threshold Reg Address Bit Field Type Setting Name Description 0x0098 LOL_FST_CLR_TH Values calculated by CBPro R_SEL_PLLA 0x0098 LOL_FST_CLR_TH R_SEL_PLLB 0x0099 LOL_FST_CLR_TH R_SEL_PLLC 0x0099 LOL_FST_CLR_TH R_SEL_PLLD Table 16.57. 0x009A LOL Enable Reg Address Bit Field Type...
  • Page 191 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.59. 0x009D Slow LOL Detection Value Reg Address Bit Field Type Setting Name Description 0x009D LOL_SLW_VAL- Values calculated by CBPro WIN_SEL_PLLA 0x009D LOL_SLW_VAL- WIN_SEL_PLLB 0x009D LOL_SLW_VAL- WIN_SEL_PLLC 0x009D LOL_SLW_VAL- WIN_SEL_PLLD Table 16.60. 0x009E LOL Set Thresholds Reg Address Bit Field Type...
  • Page 192 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.63. 0x00A1 LOL Clear Thresholds Reg Address Bit Field Type Setting Name Description 0x00A1 LOL_SLW_CLR_TH Configures the loss of lock clear thresholds. See list be- R_PLLC low for selectable values. 0x00A1 LOL_SLW_CLR_TH Configures the loss of lock clear thresholds. See list be- R_PLLD low for selectable values.
  • Page 193 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.66. 0x00A9-0x00AC LOL Clear Delay DSPLL B Reg Address Bit Field Type Setting Name Description 0x00A9 LOL_CLR_DE- 29-bit value. Sets the clear timer 0x00AA 15:8 R/W LAY_DIV256_PLLB LOL_CLR_DLY for LOL. CBPro sets this value. 0x00AA 15:8 LOL_CLR_DE-...
  • Page 194 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.70. 0x00E3 Reg Address Bit Field Type Setting Name Description 0x00E3 NVM_WRITE Write 0xC7 to initiate an NVM bank burn. Table 16.71. 0x00E4 Reg Address Bit Field Type Setting Name Description 0x00E4 NVM_READ_BANK When set, this bit will read the NVM down into the vola- tile memory.
  • Page 195 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.75. 0x00EE-0x00F1 FASTLOCK_EXTEND_PLLC Reg Address Bit Field Type Setting Name Description 0x00EE FASTLOCK_EX- 29-bit value. Set by CBPro to minimize the phase tran- TEND_PLLC sients when switching the PLL bandwidth. See FAST- LOCK_EXTEND_SCL_PLLx. 0x00EF 15:8 FASTLOCK_EX-...
  • Page 196 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.79. 0x00F8 Reg Address Bit Field Type Name Description 0x00F8 LOS_INTR Set by CBPro. 0x00F8 OOF_INTR Set by CBPro. Table 16.80. 0x00F9 Reg Address Bit Field Type Name Description 0x00F9 LOL_INTR_PLL[ Set by CBPro. D:A] 0x00F9 HOLD_INTR_PL...

  • Page 197: Registers Si5397C/D

    Si5397/96 Reference Manual Si5397C/D Register Map 16.2 Page 1 Registers Si5397C/D Table 16.82. 0x0102 Global OE Gating for all Clock Output Drivers Reg Address Bit Field Type Setting Name Description 0x0102 OUTALL_DISA- 0: Disables all output drivers BLE_LOW 1: Pass through the output enables. Table 16.83.
  • Page 198 Si5397/96 Reference Manual Si5397C/D Register Map Reg Address Bit Field Type Setting Name Description 0x0109 OUT0_SYNC_EN 0: Disable 0x011D OUT1_SYNC_EN 1: Enable 0x0127 OUT2_SYNC_EN 0x012C OUT3_SYNC_EN 0x0109 OUT0_DIS_STATE Determines the state of an output driver when disabled, selectable as 0x011D OUT1_DIS_STATE 0: Disable low 0x0127...
  • Page 199 Si5397/96 Reference Manual Si5397C/D Register Map Reg Address Bit Field Type Setting Name Description 0x010B OUT0_VDD_SEL_EN 1: Enable OUTx_VDD_SEL 0x011F OUT1_VDD_SEL_EN 0x0129 OUT2_VDD_SEL_EN 0x012E OUT3_VDD_SEL_EN 0x010B OUT0_VDD_SEL 0: 3.3 V 0x011F OUT1_VDD_SEL 1: 1.8 V 0x0129 OUT2_VDD_SEL 2: 2.5 V 0x012E OUT3_VDD_SEL 3: Reserved...
  • Page 200 Si5397/96 Reference Manual Si5397C/D Register Map Reg Address Bit Field Type Setting Name Description 0x0141 OUT_DIS_LOS- Determines if outputs are disabled during an LOSXAXB XAXB_MSK condition. 0: All outputs disabled on LOSXAXB 1: All outputs remain enabled during LOSXAXB condi- tion 0x0141 OUT_DIS_MSK_LO...

  • Page 201: Registers Si5397C/D

    Si5397/96 Reference Manual Si5397C/D Register Map 16.3 Page 2 Registers Si5397C/D Table 16.90. 0x0206 Pre-scale Reference Divide Ratio Reg Address Bit Field Type Setting Name Description 0x0206 PXAXB The divider value for the XAXB input This valid with external clock sources, not crystals. •...
  • Page 202 Si5397/96 Reference Manual Si5397C/D Register Map Register Address Description Size Same as Address 0x0226-0x022B P3_NUM 48-bit Integer Number 0x0208-0x020D 0x022C-0x022F P3_DEN 32-bit Integer Number 0x020E-0x0211 The following set of registers configure the P-dividers corresponding to each of the four input clocks seen in . ClockBuilder Pro calcu- lates the correct values for the P-dividers.
  • Page 203 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.98. 0x0234 P3 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0234 P3_FRACN_MODE P3 (IN3) input divider fractional mode. Must be set to 0xB for proper operation. 0x0234 P3_FRAC_EN P3 (IN3) input divider fractional enable 0: Integer-only division.
  • Page 204 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.102. 0x024A-0x024C R0 Divider Reg Address Bit Field Type Setting Name Description 0x024A R0_REG 24-bit Integer output divider 0x024B 15:8 R0_REG divide value = (R0_REG+1) x 2 0x024C 23:16 R0_REG To set R0 = 2, set OUT0_RDIV_FORCE2 = 1 and then the R0_REG value is irrelevant.
  • Page 205 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.105. 0x0278-0x027C OPN Identifier Reg Address Bit Field Type Setting Name Description 0x0278 OPN_ID0 OPN unique identifier. ASCII encoded. For example, with OPN: 0x0279 15:8 OPN_ID1 5347C-A12345-GM, 12345 is the OPN unique identifier: 0x027A 23:16 OPN_ID2...
  • Page 206 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.109. 0x028E-0x0291 Reg Address Bit Field Type Setting Name Description 0x028E OOF0_CLR_THR_ The OOF0 clear threshold extension (increases thresh- old precision from 2 ppm to 0.0625 ppm) 0x028F OOF1_CLR_THR_ The OOF1 clear threshold extension (increases thresh- old precision from 2 ppm to 0.0625 ppm) 0x0290 OOF2_CLR_THR_...
  • Page 207 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.113. 0x0297 FASTLOCK_DLY_ONSW_EN_PLLx Reg Address Bit Field Type Setting Name Description 0x0297 FAST- Set by CBPro. LOCK_DLY_ONSW _EN_PLLA 0x0297 FAST- LOCK_DLY_ONSW _EN_PLLB 0x0297 FAST- LOCK_DLY_ONSW _EN_PLLC 0x0297 FAST- LOCK_DLY_ONSW _EN_PLLD Table 16.114. 0x0299 FASTLOCK_DLY_ONLOL_EN_PLLx Reg Address Bit Field Type...
  • Page 208 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.116. 0x029D-0x29F FASTLOCK_DLY_ONLOL_PLLB Reg Address Bit Field Type Setting Name Description 0x029D FAST- Set by CBPro. LOCK_DLY_ON- LOL_PLLB 0x029E 15:8 FAST- LOCK_DLY_ON- LOL_PLLB 0x029F 19:16 FAST- LOCK_DLY_ON- LOL_PLLB Table 16.117. 0x02A0-0x2A2 FASTLOCK_DLY_ONLOL_PLLC Reg Address Bit Field Type Setting Name...
  • Page 209 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.119. 0x02A6-0x02A8 FASTLOCK DLY ONSW PLLA Reg Address Bit Field Type Setting Name Description 0x02A6 FAST- 20-bit value. Set by CBPro. LOCK_DLY_ONSW _PLLA 0x02A7 15:8 FAST- LOCK_DLY_ONSW _PLLA 0x02A8 19:16 FAST- LOCK_DLY_ONSW _PLLA Table 16.120.
  • Page 210 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.122. 0x02AF-0x02B1 FASTLOCK_DLY_ONSW_PLLD Reg Address Bit Field Type Setting Name Description 0x02AF FAST- 20-bit value. Set by CBPro. LOCK_DLY_ONSW _PLLD 0x02B0 15:8 FAST- LOCK_DLY_ONSW _PLLD 0x02B1 19:16 FAST- LOCK_DLY_ONSW _PLLD Table 16.123. 0x02B7 LOL_NOSIG_TIME_PLLx Reg Address Bit Field Type...
  • Page 211 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.126. 0x02BC Reg Address Bit Field Type Setting Name Description 0x02BC LOS_CMOS_MIN_ Set by CBPro. PER_EN silabs.com | Building a more connected world. Rev. 0.9 | 211...

  • Page 212: Registers Si5397C/D

    Si5397/96 Reference Manual Si5397C/D Register Map 16.4 Page 3 Registers Si5397C/D Table 16.127. 0x0302-0x0307 N0 Numerator Reg Address Bit Field Type Setting Name Description 0x0302 N0_NUM N Output Divider Numerator. 44-bit 0x0303 15:8 Integer. 0x0304 23:16 0x0305 31:24 0x0306 39:32 0x0307 43:40 Table 16.128.
  • Page 213 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.131. 0x0338 All DSPLL Internal Dividers Update Bit Reg Address Bit Field Type Setting Name Description 0x0338 N_UPDATE Writing a 1 to this bit will update all DSPLL internal di- vider values. When this bit is written, all other bits in this register must be written as zeros.

  • Page 214: Registers Si5397C/D

    Si5397/96 Reference Manual Si5397C/D Register Map 16.5 Page 4 Registers Si5397C/D Table 16.132. 0x0407 DSPLL A Active Input Reg Address Bit Field Type Setting Name Description 0x0407 IN_PLLA_ACTV Currently selected DSPLL input clock. 0: IN0 1: IN1 2: IN2 3: IN3 Table 16.133.
  • Page 215 Si5397/96 Reference Manual Si5397C/D Register Map BWx_PLLA, FAST_BWx_PLLA, and BWx_HO_PLLA parameters to take effect. Note that individual SOFT_RST_PLLA (0x001C[1]) does not update the bandwidth parameters. Table 16.135. 0x0415-0x041B MA Divider Numerator for DSPLL A Reg Address Bit Field Type Setting Name Description 0x0415 M_NUM_PLLA...
  • Page 216 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.139. 0x0422 DSPLL A FINC/FDEC Control Reg Address Bit Field Type Setting Name Description 0x0422 M_FSTEP_MSK_P 0: To enable FINC/FDEC updates. 1: To disable FINC/FDEC updates. 0x0422 M_FSTEP_DEN_PL Set by CBPro. Table 16.140. 0x0423-0x0429 DSPLLA MA Divider Frequency Step Word Reg Address Bit Field Type...
  • Page 217 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.143. 0x042C Holdover Exit Control Reg Address Bit Field Type Setting Name Description 0x042C HOLD_EN_PLLA Holdover Enable 0: Holdover Disabled 1: Holdover Enabled 0x042C HOLD_RAMP_BYP Set by CBPro. _PLLA 0x042C HOLDEX- Holdover Exit Bandwidth select. Selects the exit band- IT_BW_SEL1_PLLA width from Holdover when ramped exit is disabled (HOLD_RAMP_BYP_PLLA = 1).
  • Page 218 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.148. 0x0432 Reg Address Bit Field Type Setting Name Description 0x0432 HOLD_15M_CYC_ Value calculated by CBPro COUNT_PLLA 0x0433 15:8 HOLD_15M_CYC_ COUNT_PLLA 0x0434 23:16 HOLD_15M_CYC_ COUNT_PLLA Table 16.149. 0x0435 DSPLL A Force Holdover Reg Address Bit Field Type Setting Name...
  • Page 219 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.152. 0x0438 DSPLL A Clock Inputs 0 and 1 Priority Reg Address Bit Field Type Setting Name Description 0x0438 IN0_PRIORI- The priority for clock input 0 is: TY_PLLA 0: No priority 1: For priority 1 2: For priority 2 3: For priority 3 4: For priority 4...
  • Page 220 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.154. 0x043A Hitless Switching Mode Reg Address Bit Field Type Setting Name Description 0x043A HSW_MODE_PLLA 1: Default setting, do not modify 0,2,3: Reserved 0x043A HSW_PHMEAS_CT 0: Default setting, do not modify RL_PLLA 1,2,3: Reserved Table 16.155.
  • Page 221 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.159. 0x0442-0x0444 Reg Address Bit Field Type Setting Name Description 0x0442 FINE_ADJ_OVR_P Set by CBPro 0x0443 15:8 FINE_ADJ_OVR_P 0x0444 17:16 FINE_ADJ_OVR_P Table 16.160. 0x0445 Reg Address Bit Field Type Setting Name Description 0x0445 FORCE_FINE_ADJ Set by CBPro _PLLA...
  • Page 222 Si5397/96 Reference Manual Si5397C/D Register Map Reg Address Bit Field Type Setting Name Description 0x049B HOLD_FRZ_WITH_ Set by CBPro. INTONLY_PLLA 0x049B HOLDEX- Set by CBPro. IT_BW_SEL0_PLLA 0x049B HOLDEX- Set by CBPro. IT_STD_BO_PLLA Table 16.165. 0x049C Reg Address Bit Field Type Setting Name Description 0x049C...
  • Page 223 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.169. 0x04AC-0x04B2 Reg Address Bit Field Type Setting Name Description 0x04AC OUT_MAX_LIM- Set by CBPro. IT_EN_PLLA 0x04AC HOLD_SET- Set by CBPro. TLE_DET_EN_PLL 0x04AD 15:0 OUT_MAX_LIM- Set by CBPro. IT_LMT_PLLA 0x04B1 15:0 HOLD_SET- Set by CBPro. TLE_TAR- GET_PLLA silabs.com | Building a more connected world.

  • Page 224: Registers Si5397C/D

    Si5397/96 Reference Manual Si5397C/D Register Map 16.6 Page 5 Registers Si5397C/D Table 16.170. 0x0507 DSPLL B Active Input Reg Address Bit Field Type Setting Name Description 0x0507 IN_PLLB_ACTV Currently selected DSPLL input clock. 0: IN0 1: IN1 2: IN2 3: IN3 Table 16.171.
  • Page 225 Si5397/96 Reference Manual Si5397C/D Register Map the BWx_PLLB, FAST_BWx_PLLB, and BWx_HO_PLLB parameters to take effect. Note that individual SOFT_RST_PLLB (0x001C[2]) does not update the bandwidth parameters. Table 16.173. 0x0515-0x051B MB Divider Numerator for DSPLL B Reg Address Bit Field Type Setting Name Description 0x0515...
  • Page 226 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.177. 0x0522 DSPLL B FINC/FDEC Control Reg Address Bit Field Type Setting Name Description 0x0522 M_FSTEP_MSK_P 0: To enable FINC/FDEC updates 1: To disable FINC/FDEC updates 0x0522 M_FSTEPW_DEN_ 0: Modify numerator PLLB 1: Modify denominator Table 16.178.
  • Page 227 Si5397/96 Reference Manual Si5397C/D Register Map Reg Address Bit Field Type Setting Name Description 0x052B FAST- 0: For normal operation LOCK_MAN_PLLB 1: For force fast lock Table 16.181. 0x052C DSPLL B Holdover Control Reg Address Bit Field Type Setting Name Description 0x052C HOLD_EN_PLLB...
  • Page 228 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.186. 0x0532 Reg Address Bit Field Type Setting Name Description 0x0532 HOLD_15M_CYC_ Set by CBPro. COUNT_PLLB 0x0533 15:8 HOLD_15M_CYC_ COUNT_PLLB 0x0534 23:16 HOLD_15M_CYC_ COUNT_PLLB Table 16.187. 0x0535 DSPLL B Force Holdover Reg Address Bit Field Type Setting Name...
  • Page 229 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.190. 0x0538 DSPLL B Clock Inputs 0 and 1 Priority Reg Address Bit Field Type Setting Name Description 0x0538 IN0_PRIORI- The priority for clock input 0 is: TY_PLLB 0: No priority 1: For priority 1 2: For priority 2 3: For priority 3 4: For priority 4...
  • Page 230 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.192. 0x053A DSPLL B Hitless Switching Mode Reg Address Bit Field Type Setting Name Description 0x053A HSW_MODE_PLLB 1:Default setting, do not modify 0,2,3: Reserved 0x053A HSW_PHMEAS_CT 0: Default setting, do not modify RL_PLLB 1,2,3: Reserved Table 16.193.
  • Page 231 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.197. 0x0542-0x0544 FINE_ADJ_OVR_PLLB Reg Address Bit Field Type Setting Name Description 0x0542 FINE_ADJ_OVR_P Set by CBPro. 0x0543 15:8 FINE_ADJ_OVR_P 0x0544 17:16 FINE_ADJ_OVR_P Table 16.198. 0x0545 FORCE_FINE_ADJ_PLLB Reg Address Bit Field Type Setting Name Description 0x0545 FORCE_FINE_ADJ...
  • Page 232 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.202. 0x059B HOLDEXIT_BW_SEL0_PLLB Reg Address Bit Field Type Setting Name Description 0x059B Set by CBPro. IT_LP_CLOSE_HO _PLLB 0x059B HO_SKIP_PHASE_ PLLB 0x059B HOLD_PRE- SERVE_HIST_PLL 0x059B HOLD_FRZ_WITH_ INTONLY_PLLB 0x059B HOLDEX- IT_BW_SEL0_PLLB 0x059B HOLDEX- IT_STD_BO_PLLB Table 16.203. 0x059C Reg Address Bit Field Type...
  • Page 233 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.205. 0x05A4-0x05A5 Reg Address Bit Field Type Setting Name Description 0x05A4 HSW_LIMIT_PLLB Set by CBPro. 0x05A5 HSW_LIMIT_AC- Set by CBPro. TION_PLLB Table 16.206. 0x05A6 Reg Address Bit Field Type Setting Name Description 0x05A6 RAMP_STEP_SIZE _PLLB 0x05A6...

  • Page 234: Registers Si5397C/D

    Si5397/96 Reference Manual Si5397C/D Register Map 16.7 Page 6 Registers Si5397C/D Table 16.208. 0x0607 DSPLL C Active Input Reg Address Bit Field Type Setting Name Description 0x0607 IN_PLLC_ACTV Currently selected DSPLL input clock. 0: IN0 1: IN1 2: IN2 3: IN3 Table 16.209.
  • Page 235 Si5397/96 Reference Manual Si5397C/D Register Map This group of registers determines the DSPLL Fastlock bandwidth. In Clock Builder Pro, it is selectable from 200 Hz to 4 kHz in factors of roughly 2x each. Clock Builder Pro will then determine the values for each of these registers. Either a full device SOFT_RST_ALL (0x001C[0]) or the BW_UPDATE_PLLC bit (reg 0x0614[0]) must be used to cause all of the BWx_PLLC, FAST_BWx_PLLC, and BWx_HO_PLLC parameters to take effect.
  • Page 236 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.215. 0x0622 DSPLL C FINC/FDEC Control Reg Address Bit Field Type Setting Name Description 0x0622 M_FSTEP_MSK_P 0: To enable FINC/FDEC updates. 1: To disable FINC/FDEC updates. 0x0622 M_FSTEPW_DEN_ 0: Modify numerator PLLC 1: Modify denominator Table 16.216.
  • Page 237 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.219. 0x062C DSPLL C Holdover Control Reg Address Bit Field Type Setting Name Description 0x062C HOLD_EN_PLLC 0: Holdover disabled 1: Holdover enabled 0x062C HOLD_RAMP_BYP Must be set to 1 for normal operation. _PLLC 0x062C HOLDEX- 0: Use Fastlock bandwidth for Holdover Entry/Exit (de-...
  • Page 238 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.224. 0x0632-0x0634 Reg Address Bit Field Type Setting Name Description 0x0632 HOLD_15M_CYC_ Set by CBPro. COUNT_PLLC 0x0633 15:8 HOLD_15M_CYC_ COUNT_PLLC 0x0634 23:16 HOLD_15M_CYC_ COUNT_PLLC Table 16.225. 0x0635 DSPLL C Force Holdover Reg Address Bit Field Type Setting Name...
  • Page 239 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.228. 0x0638 DSPLL C Clock Inputs 0 and 1 Priority Reg Address Bit Field Type Setting Name Description 0x0638 IN0_PRIORI- The priority for clock input 0 is: TY_PLLC 0: No priority 1: For priority 1 2: For priority 2 3: For priority 3 4: For priority 4...
  • Page 240 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.230. 0x063A Hitless Switching Mode Reg Address Bit Field Type Setting Name Description 0x063A HSW_MODE_PLLC 1:Default setting, do not modify 0,2,3: Reserved 0x063A HSW_PHMEAS_CT 0: Default setting, do not modify RL_PLLC 1,2,3: Reserved Table 16.231.
  • Page 241 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.235. 0x0642-0x0644 Reg Address Bit Field Type Setting Name Description 0x0642 FINE_ADJ_OVR_P Set by CBPro. 0x0643 15:8 FINE_ADJ_OVR_P 0x0644 17:16 FINE_ADJ_OVR_P Table 16.236. 0x0645 Reg Address Bit Field Type Setting Name Description 0x0645 FORCE_FINE_ADJ Set by CBPro.
  • Page 242 Si5397/96 Reference Manual Si5397C/D Register Map Reg Address Bit Field Type Setting Name Description 0x069B HOLD_FRZ_WITH_ Set by CBPro. INTONLY_PLLC 0x069B HOLDEX- Set by CBPro. IT_BW_SEL0_PLL 0x069B HOLDEX- Set by CBPro. IT_STD_BO_PLLC Table 16.241. 0x069C Reg Address Bit Field Type Setting Name Description 0x069C...
  • Page 243 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.244. 0x06A6 Reg Address Bit Field Type Setting Name Description 0x06A6 RAMP_STEP_SIZE Set by CBPro. _PLLC 0x06A6 RAMP_SWITCH_E N_PLLC Table 16.245. 0x06AC-0x06B2 Reg Address Bit Field Type Setting Name Description 0x06AC OUT_MAX_LIM- Set by CBPro. IT_EN_PLLC 0x06AC HOLD_SET-...

  • Page 244: Registers Si5397C/D

    Si5397/96 Reference Manual Si5397C/D Register Map 16.8 Page 7 Registers Si5397C/D Note that register addresses for Page 7 DSPLL D Registers 0x0709–0x074D are incremented relative to similar DSPLL A/B/C address- es on Pages 4, 5, and 6. For example, Register 0x0709 has the equivalent function to Registers 0x0408/0x0508/0x0608. Table 16.246.
  • Page 245 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.248. 0x070F-0x0715 DSPLL D Fast Lock Loop Bandwidth Reg Address Bit Field Type Setting Name Description 0x070F FAST- Parameters that create the fast lock PLL bandwidth LOCK_BW0_PLLD 0x0710 FAST- LOCK_BW_1PLLD 0x0711 FAST- LOCK_BW2_PLLD 0x0712 FAST- LOCK_BW3_PLLD...
  • Page 246 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.251. 0x0721 M Divider Update Bit for PLL B Reg Address Bit Field Type Setting Name Description 0x0721 M_UPDATE_PLLD Must write a 1 to this bit to cause PLL D M divider changes to take effect. Bits 7:1 of this register have no function and can be written to any value.
  • Page 247 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.255. 0x072B DSPLL D Input Clock Select Reg Address Bit Field Type Setting Name Description 0x072B IN_SEL_PLLD 0: For IN0 1: For IN1 2: For IN2 3: For IN3 4–7: Reserved This is the input clock selection for manual register based clock selection. Table 16.256.
  • Page 248 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.259. 0x072F DSPLL D Holdover History Average Length Reg Address Bit Field Type Setting Name Description 0x072F HOLD_HIST_LEN_ 5- bit value PLLD The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length. The average frequency is then used as the holdover frequency.
  • Page 249 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.264. 0x0737 DSPLLD Input Clock Switching Control Reg Address Bit Field Type Setting Name Description 0x0737 CLK_SWITCH_MO Clock Selection Mode DE_PLLD 0: Manual 1: Automatic, non-revertive 2: Automatic, revertive 3: Reserved 0x0737 HSW_EN_PLLD 0: Glitchless switching mode (phase buildout turned off) 1: Hitless switching mode (phase buildout turned on) Table 16.265.
  • Page 250 Si5397/96 Reference Manual Si5397C/D Register Map Reg Address Bit Field Type Setting Name Description 0x0739 IN1_PRIORI- The priority for clock input 1 is: TY_PLLD 0: No priority 1: For priority 1 2: For priority 2 3: For priority 3 4: For priority 4 5–7: Reserved Table 16.267.
  • Page 251 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.269. 0x073C-0x073D Hitless Switching Phase Threshold Reg Address Bit Field Type Setting Name Description 0x073C HSW_PHMEAS_TH 10-bit value. Set by CBPro. R_PLLD 0x073D HSW_PHMEAS_TH R_PLLD Table 16.270. 0x073E Reg Address Bit Field Type Setting Name Description 0x073E...
  • Page 252 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.274. 0x0746 Reg Address Bit Field Type Setting Name Description 0x0746 FORCE_FINE_ADJ Set by CBPro. _PLLD Table 16.275. 0x0789-0x078A Reg Address Bit Field Type Setting Name Description 0x0789 PFD_EN_DE- Set by CBPro. LAY_PLLD 0x078A 12:8 PFD_EN_DE-...
  • Page 253 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.279. 0x079D-0x07A2 DSPLL Holdover Exit Bandwidth for DSPLL D Reg Address Bit Field Type Setting Name Description 0x079D HOLDEX- DSPLL D Fastlock Bandwidth parameters. IT_BW0_PLLD 0x079E HOLDEX- IT_BW1_PLLD 0x079F HOLDEX- IT_BW2_PLLD 0x07A0 HOLDEX- IT_BW3_PLLD 0x07A1 HOLDEX-...

  • Page 254: Registers Si5397C/D

    Si5397/96 Reference Manual Si5397C/D Register Map 16.9 Page 9 Registers Si5397C/D Table 16.283. 0x090E XAXB Configuration Reg Address Bit Field Type Setting Name Description 0x090E XAXB_EXTCLK_EN Selects between the XTAL or external reference clock on the XA/XB pins. Default is 0, XTAL. Set to 1 to use an external reference oscillator.

  • Page 255: Page A Registers Si5397C/D

    Si5397/96 Reference Manual Si5397C/D Register Map Table 16.288. 0x095E MXAXB Fractional Mode Reg Address Bit Field Type Setting Name Description 0x095E MXAXB_INTEGER 0: Integer MXAXB 1: Fractional MXAXB 16.10 Page A Registers Si5397C/D Table 16.289. 0x0A03 Enable DSPLL Internal Divider Clocks Reg Address Bit Field Type...

  • Page 256: Page B Registers Si5397C/D

    Si5397/96 Reference Manual Si5397C/D Register Map 16.11 Page B Registers Si5397C/D Table 16.292. 0x0B24 Reserved Control Reg Address Bit Field Type Name Description 0x0B24 RESERVED Internal use for initilization. See CBPro. Table 16.293. 0x0B25 Reserved Control Reg Address Bit Field Type Name Description...
  • Page 257 Si5397/96 Reference Manual Si5397C/D Register Map Reg Address Bit Field Type Name Description 0x0B44 FRACN_CLK_DIS_ Clock disable for the fractional divide of the M divider in PLLD PLLD. Must be set to a 0 if this M divider has a fraction- al value.
  • Page 258 Si5397/96 Reference Manual Si5397C/D Register Map ClockBuilder Pro handles these bits when changing settings for all portions of the device. This control bit is only needed when changing the settings for only a portion of the device while the remaining portion of the device operates undisturbed. Table 16.300.

  • Page 259: Page C Registers Si5397C/D

    Si5397/96 Reference Manual Si5397C/D Register Map 16.12 Page C Registers Si5397C/D Table 16.302. 0x0C02 Reg Address Bit Field Type Name Description 0x0C02 VAL_DIV_CTL0 Set by CBPro 0x0C02 VAL_DIV_CTL1 Set by CBPro Table 16.303. 0x0C03 Reg Address Bit Field Type Name Description 0x0C03 IN_CLK_VAL_PWR_UP_DIS...
  • Page 260 Si5397/96 Reference Manual Si5397C/D Register Map Table 16.310. 0x0C0B Reg Address Bit Field Type Name Description 0x0C0B IN_CLK_VAL_EN Set by CBPro _PLLD Table 16.311. 0x0C0C Reg Address Bit Field Type Name Description 0x0C0C IN_CLK_VAL_TIME_P Set by CBPro silabs.com | Building a more connected world. Rev.

  • Page 261: Si5396 Register Map

    Si5397/96 Reference Manual Si5396 Register Map 17. Si5396 Register Map 17.1 Page 0 Registers Si5396 Table 17.1. 0x0000 Die Rev Reg Address Bit Field Type Setting Name Description 0x0000 DIE_REV 4- bit Die Revision Number Table 17.2. 0x0001 Page Reg Address Bit Field Type Setting Name...
  • Page 262 Si5397/96 Reference Manual Si5396 Register Map Table 17.6. 0x0006–0x0008 TOOL_VERSION Reg Address Bit Field Type Name Description 0x0006 TOOL_VERSION[3:0] Special 0x0006 TOOL_VERSION[7:4] Revision 0x0007 TOOL_VERSION[15:8] Minor[7:0] 0x0008 TOOL_VERSION[15:8] Minor[8] 0x0008 TOOL_VERSION[16] Major 0x0008 TOOL_VERSION[13:17] Tool. 0 for ClockBuilder Pro Table 17.7. 0x0009–0x000A NVM Identifier, Pkg ID Reg Address Bit Field Type...
  • Page 263 Si5397/96 Reference Manual Si5396 Register Map Bit 1 is the LOS status monitor for the XTAL or REFCLK at the XA/XB pins. Bit 3 is the XAXB problem status monitor and may indicate the XAXB input signal has excessive jitter, ringing, or low amplitude. Bit 5 indicates a timeout error when using SMBUS with the I serial port.
  • Page 264 Si5397/96 Reference Manual Si5396 Register Map Table 17.14. 0x0012 Sticky OOF and LOS Flags Reg Address Bit Field Type Setting Name Description 0x0012 LOS_FLG 1 if the clock input is LOS 0x0012 OOF_FLG 1 if the clock input is OOF These are sticky flag versions of 0x000D.
  • Page 265 Si5397/96 Reference Manual Si5396 Register Map Reg Address Bit Field Type Setting Name Description 0x0017 LOS- REF_INTR_MSK 0x0017 XAXB_ERR_INTR_ 0x0017 SMB_TMOUT_INT 1 to mask out SMBUS_TIMEOUT. R_MSK 0x0017 Reserved Factory set to 1 to mask reserved bit from causing an interrupt.
  • Page 266 Si5397/96 Reference Manual Si5396 Register Map Table 17.22. 0x001C Soft Reset and Calibration Reg Address Bit Field Type Setting Name Description 0x001C SOFT_RST_ALL 0: No effect 1: initialize and calibrate the entire device. 0x001C SOFT_RST_PLLA 1 initialize and calibrate DSPLLA 0x001C SOFT_RST_PLLB 1 initialize and calibrate DSPLLB...
  • Page 267 Si5397/96 Reference Manual Si5396 Register Map By default ClockBuilder Pro sets OE0 controlling all outputs and OE1 unused. OUTALL_DISABLE_LOW 0x0102[0] must be high (ena- bled) to observe the effects of OE0 and OE1. Note that the OE0 and OE1 register bits (active high) have inverted logic sense from the pins (active low).
  • Page 268 Si5397/96 Reference Manual Si5396 Register Map Table 17.30. 0x0030-0x0031 LOS1 Trigger Threshold Reg Address Bit Field Type Setting Name Description 0x0030 LOS1_TRG_THR 16-bit Threshold Value 0x0031 15:8 LOS1_TRG_THR ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 1, given a particular frequency plan. Table 17.31.
  • Page 269 Si5397/96 Reference Manual Si5396 Register Map Table 17.36. 0x003C-0x003D LOS3 Clear Threshold Reg Address Bit Field Type Setting Name Description 0x003C LOS3_CLR_THR 16-bit Threshold Value 0x003D 15:8 LOS3_CLR_THR ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 3, given a particular frequency plan. Table 17.37.
  • Page 270 Si5397/96 Reference Manual Si5396 Register Map Table 17.40. 0x0041-0X0045 OOF Divider Select Reg Address Bit Field Type Setting Name Description 0x0041 OOF0_DIV_SEL Sets a divider for the OOF circuitry for each input clock OOFx_DIV_SEL 0,1,2,3. The divider value is 2 .
  • Page 271 Si5397/96 Reference Manual Si5396 Register Map Table 17.44. 0x0050 OOF_ON_LOS Reg Address Bit Field Type Setting Name Description 0x0050 OOF_ON_LOS Set by CBPro Table 17.45. 0x0051-0x0054 Fast Out of Frequency Set Threshold Reg Address Bit Field Type Setting Name Description 0x0051 FAST_OOF0_SET_ (1 + Value) x 1000 ppm...
  • Page 272 Si5397/96 Reference Manual Si5396 Register Map Table 17.48. 0x005A-0x005D OOF0 Ratio for Reference Reg Address Bit Field Type Setting Name Description 0x005A OOF0_RATIO_REF Values calculated by CBPro 0x005B 15:8 OOF0_RATIO_REF 0x005C 23:16 OOF0_RATIO_REF 0x005D 25:24 OOF0_RATIO_REF Table 17.49. 0x005E-0x0061 OOF1 Ratio for Reference Reg Address Bit Field Type...
  • Page 273 Si5397/96 Reference Manual Si5396 Register Map Table 17.53. 0x0093 Fast LOL Detection Window Reg Address Bit Field Type Setting Name Description 0x0093 LOL_FST_DET- Values calculated by ClockBuilder Pro WIN_SEL_PLLA 0x0093 LOL_FST_DET- WIN_SEL_PLLB Table 17.54. 0x0095 Reg Address Bit Field Type Setting Name Description 0x0095...
  • Page 274 Si5397/96 Reference Manual Si5396 Register Map Table 17.58. 0x009B Slow LOL Detection Window Reg Address Bit Field Type Setting Name Description 0x009B 3:00 LOL_SLW_DET- Values calculated by CBPro WIN_SEL_PLLB 0x009B 7:04 LOL_SLW_DET- WIN_SEL_PLLA Table 17.59. 0x009D LOL Enable Reg Address Bit Field Type Setting Name...
  • Page 275 Si5397/96 Reference Manual Si5396 Register Map Table 17.63. 0x00A4-0x00A7 LOL Clear Delay DSPLL A Reg Address Bit Field Type Setting Name Description 0x00A4 LOL_CLR_DE- 29-bit value LAY_DIV256_PLLA 0x00A5 15:8 LOL_CLR_DE- LAY_DIV256_PLLA 0x00A6 23:16 LOL_CLR_DE- LAY_DIV256_PLLA 0x00A7 28:24 LOL_CLR_DE- LAY_DIV256_PLLA Table 17.64. 0x00A9-0x00AC LOL Clear Delay DSPLL B Reg Address Bit Field Type...
  • Page 276 Si5397/96 Reference Manual Si5396 Register Map Table 17.67. 0x00E6-0x00E9 FASTLOCK_EXTEND_PLLA Reg Address Bit Field Type Setting Name Description 0x00E6 FASTLOCK_EX- 29-bit value. Set by CBPro to minimize the phase tran- TEND_PLLA sients when switching the PLL bandwidth. See FAST- LOCK_EXTEND_SCL_PLLx. 0x00E7 15:8 FASTLOCK_EX-...
  • Page 277 Si5397/96 Reference Manual Si5396 Register Map Table 17.71. 0x00F8 Reg Address Bit Field Type Name Description 0x00F8 LOS_INTR Set by CBPro. 0x00F8 OOF_INTR Set by CBPro. Table 17.72. 0x00F9 Reg Address Bit Field Type Name Description 0x00F9 LOL_INTR_PLL[ Set by CBPro. B:A] 0x00F9 HOLD_INTR_PL...

  • Page 278: Registers Si5396

    Si5397/96 Reference Manual Si5396 Register Map 17.2 Page 1 Registers Si5396 Table 17.74. 0x0102 Global OE Gating for all Clock Output Drivers Reg Address Bit Field Type Setting Name Description 0x0102 OUTALL_DISA- 0: Disables all output drivers BLE_LOW 1: Pass through the output enables Table 17.75.
  • Page 279 Si5397/96 Reference Manual Si5396 Register Map Reg Address Bit Field Type Setting Name Description 0x0113 OUT0_SYNC_EN 0: Disable 0x0118 OUT1_SYNC_EN 1: Enable 0x0127 OUT2_SYNC_EN 0x012C OUT3_SYNC_EN 0x0113 OUT0_DIS_STATE Determines the state of an output driver when disabled, selectable as 0x0118 OUT1_DIS_STATE 0: Disable low 0x0127...
  • Page 280 Si5397/96 Reference Manual Si5396 Register Map Reg Address Bit Field Type Setting Name Description 0x0115 OUT0_VDD_SEL_- 1: Enable OUTx_VDD_SEL 0x011A OUT1_VDD_SEL_- 0x0129 0x012E OUT2_VDD_SEL_- OUT3_VDD_SEL_- 0x0115 OUT0_VDD_SEL 0: 3.3 V 0x011A OUT1_VDD_SEL 1: 1.8 V 0x0129 OUT2_VDD_SEL 2: 2.5 V 0x012E OUT3_VDD_SEL 3: Reserved...
  • Page 281 Si5397/96 Reference Manual Si5396 Register Map Table 17.81. 0x0141 Output Disable Mask for LOS XAXB Reg Address Bit Field Type Setting Name Description 0x0141 OUT_DIS_MSK_PL 0x0141 OUT_DIS_MSK_PL 0x0141 OUT_DIS_LOL_MS 0x0141 OUT_DIS_LOS- Determines if outputs are disabled during an LOSXAXB XAXB_MSK condition.

  • Page 282: Registers Si5396

    Si5397/96 Reference Manual Si5396 Register Map 17.3 Page 2 Registers Si5396 Table 17.83. 0x0206 XAXB Clock Input Reference Divide Value Reg Address Bit Field Type Setting Name Description 0x0206 PXAXB The divider value for the XAXB input This can be used with external clock sources, not crystals. 0 = pre-scale value 1 1 = pre-scale value 2 2 = pre-scale value 4...
  • Page 283 Si5397/96 Reference Manual Si5396 Register Map Register Address Description Size Same as Address 0x0226-0x022B P3_NUM 48-bit Integer Number 0x0208-0x020D 0x022C-0x022F P3_DEN 32-bit Integer Number 0x020E-0x0211 The following set of registers configure the P-dividers corresponding to each of the four input clocks seen in . ClockBuilder Pro calcu- lates the correct values for the P-dividers.
  • Page 284 Si5397/96 Reference Manual Si5396 Register Map Table 17.91. 0x0234 P3 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0234 P3_FRACN_MODE P3 (IN3) input divider fractional mode. Must be set to 0xB for proper operation. 0x0234 P3_FRAC_EN P3 (IN3) input divider fractional enable 0: Integer-only division.
  • Page 285 Si5397/96 Reference Manual Si5396 Register Map Table 17.95. 0x0250-0x0252 R0 Divider Reg Address Bit Field Type Setting Name Description 0x0250 R0_REG 24-bit Integer divider 0x0251 15:8 R0_REG divider value = (R0_REG+1) x 2 0x0252 23:16 R0_REG To set R0 = 2, set OUT0_RDIV_FORCE2 = 1 and then the R0_REG value is irrelevant.
  • Page 286 Si5397/96 Reference Manual Si5396 Register Map Table 17.98. 0x0278- 0x027D OPN Identifier Reg Address Bit Field Type Setting Name Description 0x0278 OPN_ID0 OPN unique identifier. ASCII encoded. For example, with OPN: 0x0279 15:8 OPN_ID1 5346C-A12345-GM, 12345 is the OPN unique identifier: 0x027A 23:16 OPN_ID2...
  • Page 287 Si5397/96 Reference Manual Si5396 Register Map Table 17.102. 0x0292-0x0293 Reg Address Bit Field Type Setting Name Description 0x0292 OOF_STOP_ON_L Set by CBPro. 0x0293 OOF_CLEAR_ON_ Set by CBPro. Table 17.103. 0x028E-0x0291 Reg Address Bit Field Type Setting Name Description 0x028E OOF0_CLR_THR_ The OOF0 clear threshold extension (increases thresh- old precision from 2 ppm to 0.0625 ppm) 0x028F...
  • Page 288 Si5397/96 Reference Manual Si5396 Register Map Table 17.107. 0x0299 Reg Address Bit Field Type Setting Name Description 0x0299 FAST- Set by CBPro. LOCK_DLY_ON- LOL_EN_PLLA 0x0299 FAST- LOCK_DLY_ON- LOL_EN_PLLB Table 17.108. 0x029A-0x29C Reg Address Bit Field Type Setting Name Description 0x029A FAST- Set by CBPro.
  • Page 289 Si5397/96 Reference Manual Si5396 Register Map Table 17.111. 0x02A9-0x2AB Reg Address Bit Field Type Setting Name Description 0x02A9 FAST- Set by CBPro. LOCK_DLY_ONSW _PLLB 0x02AA 15:8 FAST- LOCK_DLY_ONSW _PLLB 0x02AB 19:16 FAST- LOCK_DLY_ONSW _PLLB Table 17.112. 0x02B7 Reg Address Bit Field Type Setting Name Description...

  • Page 290: Registers Si5396

    Si5397/96 Reference Manual Si5396 Register Map 17.4 Page 3 Registers Si5396 Table 17.116. 0x0302-0x0307 N0 Numerator Reg Address Bit Field Type Setting Name Description 0x0302 N0_NUM N Output Divider Numerator. 44-bit 0x0303 15:8 Integer. 0x0304 23:16 0x0305 31:24 0x0306 39:32 0x0307 43:40 Table 17.117.
  • Page 291 Si5397/96 Reference Manual Si5396 Register Map Table 17.120. 0x0338 All DSPLL Internal Dividers Update Bit Reg Address Bit Field Type Name Description 0x0338 N_UPDATE Writing a 1 to this bit will update all DSPLL internal di- vider values. When this bit is written, all other bits in this register must be written as zeros.
  • Page 292 Si5397/96 Reference Manual Si5396 Register Map 17.5 Page 4 Registers Si5396 Table 17.121. 0x0407 DSPLL A Active Input Reg Address Bit Field Type Setting Name Description 0x0407 IN_PLLA_ACTV Currently selected DSPLL input clock 0: IN0 1: IN1 2: IN2 3: IN3 Table 17.122.
  • Page 293 Si5397/96 Reference Manual Si5396 Register Map The fast lock loop bandwidth values are calculated by ClockBuilder Pro and are written into these registers. Note that a 1 must be writ- ten to BW_UPDATE_PLLA to update the BW parameters for this DSPLL. Soft Reset does not update the DSPLL bandwidth parame- ters.
  • Page 294 Si5397/96 Reference Manual Si5396 Register Map Table 17.128. 0x0422 DSPLL A FINC/FDEC Masking Reg Address Bit Field Type Setting Name Description 0x0422 M_FSTEP_MSK_P 0: To enable FINC/FDEC updates 1: To disable FINC/FDEC updates Table 17.129. 0x0423-0x0429 DSPLLA M Divider Frequency Step Word Reg Address Bit Field Type...
  • Page 295 Si5397/96 Reference Manual Si5396 Register Map Table 17.132. 0x042E DSPLL A Holdover History Average Length Reg Address Bit Field Type Setting Name Description 0x042E HOLD_HIST_LEN_ 5- bit value PLLA The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length. The average frequency is then used as the holdover frequency.
  • Page 296 Si5397/96 Reference Manual Si5396 Register Map Table 17.137. 0x0436 DSPLLA Input Clock Switching Control Reg Address Bit Field Type Setting Name Description 0x0436 CLK_SWITCH_MO Clock Selection Mode DE_PLLA 0: Manual 1: Automatic, non-revertive 2: Automatic, revertive 3: Reserved 0x0436 HSW_EN_PLLA 0: Glitchless switching mode (phase buildout turned off) 1: Hitless switching mode (phase buildout turned on) Table 17.138.
  • Page 297 Si5397/96 Reference Manual Si5396 Register Map Reg Address Bit Field Type Setting Name Description 0x0438 IN1_PRIORI- The priority for clock input 1 is: TY_PLLA 0: No priority 1: For priority 1 2: For priority 2 3: For priority 3 4: For priority 4 5–7: Reserved Table 17.140.
  • Page 298 Si5397/96 Reference Manual Si5396 Register Map Table 17.142. 0x043B-0x043C Hitless Switching Phase Threshold Reg Address Bit Field Type Setting Name Description 0x043B HSW_PHMEAS_TH Set by CBPro. R_PLLA 0x043C HSW_PHMEAS_TH R_PLLA Table 17.143. 0x043D Reg Address Bit Field Type Setting Name Description 0x043D HSW_COARSE_P...
  • Page 299 Si5397/96 Reference Manual Si5396 Register Map Table 17.147. 0x0445 Reg Address Bit Field Type Setting Name Description 0x0445 FORCE_FINE_ADJ Set by CBPro _PLLA Table 17.148. 0x0488 HSW_FINE_PM_LEN_PLLA Reg Address Bit Field Type Setting Name Description 0x0488 HSW_FINE_PM_LE N_PLLA Table 17.149. 0x0489 PFD_EN_DELAY_PLLA Reg Address Bit Field Type...
  • Page 300 Si5397/96 Reference Manual Si5396 Register Map Table 17.152. 0x049C Reg Address Bit Field Type Setting Name Description 0x049C HOLDEX- Set by CBPro. IT_ST_BO_PLLA 0x049C HOLD_RAMPBP_N Set by CBPro. OHIST_PLLA Table 17.153. 0x049D-0x04A2 DSPLL Holdover Exit Bandwidth for DSPLL A Reg Address Bit Field Type Setting Name...
  • Page 301 Si5397/96 Reference Manual Si5396 Register Map 17.6 Page 5 Registers Si5396 Table 17.157. 0x0507 DSPLL B Active Input Reg Address Bit Field Type Setting Name Description 0x0507 IN_PLLB_ACTV Currently selected DSPLL input clock 0: IN0 1: IN1 2: IN2 3: IN3 Table 17.158.
  • Page 302 Si5397/96 Reference Manual Si5396 Register Map (0x001C[0]) or the BW_UPDATE_PLLB bit (reg 0x0514[0]) must be used to cause all of the BWx_PLLB, FAST_BWx_PLLB, and BWx_HO_PLLB parameters to take effect. Note that individual SOFT_RST_PLLB (0x001C[2]) does not update the bandwidth parame- ters.
  • Page 303 Si5397/96 Reference Manual Si5396 Register Map Table 17.164. 0x0522 DSPLL B FINC/FDEC Control Reg Address Bit Field Type Setting Name Description 0x0522 M_FSTEP_MSK_P 0: To enable FINC/FDEC updates 1: To disable FINC/FDEC updates 0x0522 M_FSTEPW_DEN_ PLLB Table 17.165. 0x0523-0x0529 DSPLLB MB Divider Frequency Step Word Reg Address Bit Field Type...
  • Page 304 Si5397/96 Reference Manual Si5396 Register Map Table 17.168. 0x052C DSPLL B Holdover Control Reg Address Bit Field Type Setting Name Description 0x052C HOLD_EN_PLLB 0x052C HOLD_RAMP_BYP Must be set to 1 for normal operation. _PLLB 0x052C HOLDEX- 0: To use the fastlock loop BW when exiting from hold- IT_BW_SEL1_PLLB over 1: To use the normal loop BW when exiting from hold-...
  • Page 305 Si5397/96 Reference Manual Si5396 Register Map Table 17.173. 0x0535 DSPLL B Force Holdover Reg Address Bit Field Type Setting Name Description 0x0535 FORCE_HOLD_PL 0: For normal operation 1: To force holdover Table 17.174. 0x0536 DSPLLB Input Clock Switching Control Reg Address Bit Field Type Setting Name...
  • Page 306 Si5397/96 Reference Manual Si5396 Register Map Table 17.176. 0x0538 DSPLL B Clock Inputs 0 and 1 Priority Reg Address Bit Field Type Setting Name Description 0x0538 IN0_PRIORI- The priority for clock input 0 is: TY_PLLB 0: No priority 1: For priority 1 2: For priority 2 3: For priority 3 4: For priority 4...
  • Page 307 Si5397/96 Reference Manual Si5396 Register Map Table 17.178. 0x053A DSPLL B Hitless Switching Mode Reg Address Bit Field Type Setting Name Description 0x053A HSW_MODE_PLLB 1:Default setting, do not modify 0,2,3: Reserved 0x053A HSW_PHMEAS_CT 0: Default setting, do not modify RL_PLLB 1,2,3: Reserved Table 17.179.
  • Page 308 Si5397/96 Reference Manual Si5396 Register Map Table 17.183. 0x0542-0x0544 FINE_ADJ_OVR_PLLB Reg Address Bit Field Type Setting Name Description 0x0542 FINE_ADJ_OVR_P Set by CBPro. 0x0543 15:8 FINE_ADJ_OVR_P 0x0544 17:16 FINE_ADJ_OVR_P Table 17.184. 0x0545 FORCE_FINE_ADJ_PLLB Reg Address Bit Field Type Setting Name Description 0x0545 FORCE_FINE_ADJ...
  • Page 309 Si5397/96 Reference Manual Si5396 Register Map Table 17.188. 0x059B HOLDEXIT_BW_SEL0_PLLB Reg Address Bit Field Type Setting Name Description 0x059B Set by CBPro. IT_LP_CLOSE_HO _PLLB 0x059B HO_SKIP_PHASE_ PLLB 0x059B HOLD_PRE- SERVE_HIST_PLL 0x059B HOLD_FRZ_WITH_ INTONLY_PLLB 0x059B HOLDEX- IT_BW_SEL0_PLLB 0x059B HOLDEX- IT_STD_BO_PLLB Table 17.189. 0x059C Reg Address Bit Field Type...
  • Page 310 Si5397/96 Reference Manual Si5396 Register Map Table 17.193. 0x05A0 Reg Address Bit Field Type Setting Name Description 0x05A0 HOLDEX- IT_BW3_PLLB Table 17.194. 0x05A1 Reg Address Bit Field Type Setting Name Description 0x05A1 HOLDEX- IT_BW4_PLLB Table 17.195. 0x059A2 Reg Address Bit Field Type Setting Name Description...
  • Page 311 Si5397/96 Reference Manual Si5396 Register Map 17.7 Page 9 Registers Si5396 Table 17.199. 0x090E XAXB Configuration Reg Address Bit Field Type Setting Name Description 0x090E XAXB_EXTCLK_EN Selects between the XTAL or external reference clock on the XA/XB pins. Default is 0, XTAL. Set to 1 to use an external reference oscillator.
  • Page 312 Si5397/96 Reference Manual Si5396 Register Map Table 17.204. 0x095E MXAXB Fractional Mode Reg Address Bit Field Type Setting Name Description 0x095E MXAXB_INTEGER Set by CBPro 17.8 Page A Registers Si5396 Table 17.205. 0x0A03 Enable DSPLL Internal Divider Clocks Reg Address Bit Field Type Name...
  • Page 313 Si5397/96 Reference Manual Si5396 Register Map 17.9 Page B Registers Si5396 Table 17.208. 0x0B24 Reserved Control Reg Address Bit Field Type Name Description 0x0B24 RESERVED Internal use for initilization. See CBPro. Table 17.209. 0x0B25 Reserved Control Reg Address Bit Field Type Name Description...
  • Page 314 Si5397/96 Reference Manual Si5396 Register Map Table 17.212. 0x0B46 Loss of Signal Clock Disable Reg Address Bit Field Type Name Description 0x0B46 LOS_CLK_DIS Controls the clock to the digital LOS circuitry. Must be set to 0 to enable the LOS function of the respective In- puts (IN3 IN2 IN1 IN0).
  • Page 315 Si5397/96 Reference Manual Si5396 Register Map 17.10 Page C Registers Si5396 Table 17.218. 0x0C02 Reg Address Bit Field Type Name Description 0x0C02 VAL_DIV_CTL0 Set by CBPro 0x0C02 VAL_DIV_CTL1 Set by CBPro Table 17.219. 0x0C03 Reg Address Bit Field Type Name Description 0x0C03 IN_CLK_VAL_PWR_UP_DIS...
  • Page 316 Si5397/96 Reference Manual Revision History 18. Revision History Revision 0.9 June 2019 • Updated CMOS input buffer section • Added information for internal reference devices Revision 0.1 June 2018 • Intitial Release silabs.com | Building a more connected world. Rev. 0.9 | 316...
  • Page 317 Trademark Information Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®, Gecko OS, Gecko OS Studio, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®...

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