ZYBO™ FPGA Board Reference Manual
MIO 501
1.8V
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
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Other product and company names mentioned may be trademarks of their respective owners.
Peripherals
ENET 0
USB 0
TXCK
TXD0
TXD1
TXD2
TXD3
TXCTL
RXCK
RXD0
RXD1
RXD2
RXD3
RXCTL
DATA4
DIR
STP
NXT
DATA0
DATA1
DATA2
DATA3
CLK
DATA5
DATA6
DATA7
RESETN
MDC
MDIO
Table 3. MIO Pinout.
SDIO 0
UART 1
CCLK
CMD
D0
D1
D2
D3
CD
RXD
TXD
GPIO
BTN4
BTN5
Page 8 of 26
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