Digilent ZYBO Reference Manual page 15

ZYBO™ FPGA Board Reference Manual
After power-up the PHY starts with Auto Negotiation enabled, advertising 10/100/1000 link speeds and full duplex.
If there is an Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the
Zynq not configured.
MIO53
MIO52
MIO23
MIO24
MIO25
MIO26
MIO27
MIO22
MIO17
MIO18
MIO19
MIO20
MIO21
MIO16
F16
E17
L16
PS_CLK
Zynq-7
Two status indicator LEDs are on-board near the RJ-45 connector that indicate traffic (LD7) and valid link state
(LD6). Table 5 shows the default behavior.
Function Designator
LINK LD6
ACT LD7
The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full
duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY interfaces. Since the
MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an
external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring
the interface is handled by the ZYBO board definition file.
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MDIO
MDC
RXD0/SELRGV
RXD1/TXDLY
RXD2/AN0
RXD3/AN1
RXCTL/PHY_AD2
RXC
TXD0
TXD1
TXD2
TXD3
TXCTL
TXC
INTB
PHYRSTB
CLK125
CKXTAL1
50 MHz
Oscillator
DSC1121CE5 Realtek RTL8211E
Figure 7. Ethernet PHY signals.
State
On
Blinking 0.4s ON, 2s OFF
Blinking
Table 5. Ethernet status LEDs.
RJ-45 with
magnetics
8
LED0/PHY_AD0
ACT LED (LD7)
LINK LED (LD6)
LED1/PHY_AD1
Description
Link 10/100/1000
Link, Energy Efficient Ethernet (EEE) mode
Transmitting or Receiving
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