Hdmi Source/Sink Port - Digilent ZYBO Reference Manual

ZYBO™ FPGA Board Reference Manual
Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is
available for management. The RTL8211E-VL is assigned address 00001b. With simple register read and write
commands, status information can be read out or configuration changed. The Realtek PHY follows industry-
standard register map for basic configuration.
The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed relative to the data
signals (RXD[0:3], RXCTL and TXD[0:3], TXCTL). Xilinx PCB guidelines also require this delay to be added. The
RTL8211E-VL is capable of inserting a 2ns delay on both the TXC and RXC so that board traces do not need to be
made longer.
The PHY is clocked from the same 50 MHz oscillator (IC22) that clocks the PS too. The parasitic capacitance of the
two loads is low enough to be driven from a single source.
On an Ethernet network each node needs a unique MAC address. To this end, a Microchip 24AA02E48 EEPROM is
provided on the ZYBO. On one hand it is a read-writeable EEPROM that can be accessed via I
it features a read-only memory section that comes pre-programmed with a unique identifier. This unique identifier
can be read and used as a MAC address, avoiding a possible address conflict on the network. The I
connects to the PL side and can be accessed from the PS over EMIO as well. The device address of the EEPROM is
1010000b.
For more information on using the Gigabit Ethernet MAC, refer to the Xilinx Zynq TRM (ug585).

10 HDMI Source/Sink Port

An input and output-capable HDMI Port connects to the programmable logic pins. Over this connector an HDMI or
DVI-compatible video stream can be driven in or out of the ZYBO. Encoding or decoding the HDMI/DVI video
stream needs to be implemented in logic, as well as auxiliary functions, like DDC or CEC. Depending on the actual
design, it can take the Source role driving a monitor/TV display, or behave as a Sink accepting a video stream from
any HDMI/DVI Source, like a laptop or smartphone.
On-board auxiliary buffers and electronic switches control the direction of signals that differ between Source and
Sink. These signals are summarized Table 6.
Signal Role Description
Source
Hot-plug detect; signals the
HPD
presence of a Sink to a Source
Sink
Source
5V0 Auxiliary power for Sink
Sink
The CEC function is bi-directional by definition, so it is treated the same no matter what role the port takes. If the
CEC function is not used, declare it as input and constrain it to the correct PL pin to leave other devices on the CEC
bus unaffected.
When operating as Sink, the DDC function is required to be implemented so that a connected Source can read out
important characteristics of the device. This can be done by emulating an I
logic. Likewise, in Source mode DDC can be used to find out the capabilities of the connected display.
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Direction (Zynq POW)
Input
Output
Output
Input
Table 6. HDMI signal direction in Source and Sink roles.
2
C. On the other hand
2
C interface
How to control
HDMI_OUT_EN = 1
HDMI_OUT_EN = 0
HDMI_OUT_EN = 1
HDMI_OUT_EN = 0
2
C-capable EEPROM in programmable
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