Reset Sources - Digilent ZYBO Reference Manual

ZYBO™ FPGA Board Reference Manual
2
can also be done in the codec. Configuration is read out and written by accessing the register map via I C transfers.
The register map is described in the SSM2603 datasheet.

15 Reset Sources

15.1 Power-on Reset
The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip.
This signal resets every register in the device capable of being reset. The ZYBO drives this signal from a comparator
that holds the system in reset until all power supplies are valid. Several other IC's on the ZYBO are reset by this
signal as well.
15.2 Program Push-button Switch
A PROG push switch, BTN6, toggles Zynq PROG_B. This resets the PL and causes DONE to be de-asserted. The PL
will remain unconfigured until it is reprogrammed by the processor or via JTAG.
15.3 Processor Subsystem Reset
The external system reset, labeled PS_SRST/BTN7, resets the Zynq device without disturbing the debug
environment. For example, the previous break points set by the user remain valid after system reset. Due to
security concerns, system reset erases all memory content within the PS, including the OCM. The PL is also cleared
during a system reset. System reset does not cause the boot mode strapping pins to be re-sampled.
16 Pmod Ports
Pmod ports are 2x6, right-angle, 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each
12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic
signals, as shown in Fig. 16. The VCC and Ground pins can deliver up to 1A of current, but care must be taken not
to exceed any of the power budgets of the onboard regulators or the external power supply.
VCC GND 8 signals
Pin 1
Pin 6
Pin 12
Figure 16. Pmod diagram.
Copyright Digilent, Inc. All rights reserved.
Page 24 of 26
Other product and company names mentioned may be trademarks of their respective owners.