Digilent ZYBO Reference Manual page 20

ZYBO™ FPGA Board Reference Manual
refresh frequencies falling in the 50Hz to 120Hz range. The number of lines to be displayed at a given refresh
frequency defines the horizontal "retrace" frequency. For a 640-pixel by 480-row display using a 25MHz pixel clock
and 60 +/-1Hz refresh, the signal timings shown in Fig. 11 can be derived. Timings for sync pulse width and front
and back porch intervals (porch intervals are the pre- and post-sync pulse times during which information cannot
be displayed) are based on observations taken from actual VGA displays.
Figure 11. Signal timings for a 640-pixel by 480 row display using a 25MHz pixel clock and 60Hz vertical refresh.
A VGA controller circuit, such as the one diagramed in Fig. 12, decodes the output of a horizontal-sync counter
driven by the pixel clock to generate HS signal timings. You can use this counter to locate any pixel location on a
given row. Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to
generate VS signal timings, and you can use this counter to locate any given row. These two continually running
counters can be used to form an address into video RAM. No time relationship between the onset of the HS pulse
and the onset of the VS pulse is specified, so you can arrange the counters to easily form video RAM addresses, or
to minimize decoding logic for sync pulse generation.
Horizontal
Pixel Counter
CLK
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T
fp
T
pw
Symbol Parameter
T S
Sync pulse
T disp
Display time 15.36ms
T pw
Pulse width
T fp
Front porch
T bp
Back porch
Zero
Set
Detect
Horizontal
Synch
3.84us
Reset
Detect
Figure 12. VGA display controller block diagram.
T
S
T
disp
T
bp
Horiz. Sync
Vertical Sync
Time Clocks Lines Time
16.7ms 416,800 521 32 us
384,000 480 25.6 us
64 us 1,600 2 3.84 us
320 us 8,000 10 640 ns
928 us 23,200 29 1.92 us
Zero
CE
Detect
Vertical
Counter
64us
Detect
Clks
800
640
96
16
48
HS
Set
VS
Vertical
Synch
Reset
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