Digilent ZYBO Reference Manual page 23

ZYBO™ FPGA Board Reference Manual
The digital interface of the SSM2603 is wired to the programmable logic side of the Zynq. Audio data is transferred
2
via the I S protocol. Configuration is done over an I
digital I/O are 3.3V level and connect to a 3.3V-powered FPGA bank.
SSM2603 pin Protocol
2
BCLK I
2
PBDAT I
2
PBLRC I
2
RECDAT I
2
RECLRC I
2
SDIN I
2
SCLK I
MUTE Digital Enable (Active Low)
MCLK Master Clock
The audio codec needs to be clocked from the Zynq on the MCLK pin. This master clock will be used by the audio
codec to establish the audio sampling frequency. This clock is required to be an integer multiple of the desired
sampling rate. The default settings require a master clock of 12.288 Mhz, resulting in a 48 kHz sampling rate. For
other frequencies and their respective configuration parameters, consult the SSM2603 datasheet.
The codec has two modes: master and slave, with the slave being default. In this mode, the direction of the signals
is specified in Table 8. When configured as master, the direction of BCLK, PBLRC and RECLRC is inverted. In this
mode, the codec generates the proper frequencies for these clocks. No matter where are the clocks are generated,
PBDAT needs to be driven out and RECDAT sampled in sync with them. The master clock is always driven out of the
Zynq. The timing diagram of an I
with respect to the left/right clock changing state. Audio samples are transmitted MSB first, noted as 1 in the
diagram.
BCLK
PB/RECLRC
N 1
PB/RECDAT
The digital mute signal (MUTE) is active-low, with a pull-down resistor. This means that when not used in the
design, it will stay low and the analog outputs of the codec will stay muted. To enable the analog outputs, drive
this signal high.
To use the audio codec in a design with non-default settings, it needs to be configured over I
needs to be established by configuring the (de)multiplexers and amplifiers in the codec. Some digital processing
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2
C bus. The device address of the SSM2603 is 0011010b. All
S (Serial Clock)
S (Playback Data)
S (Playback Channel Clock)
S (Record Data)
S (Record Channel Clock)
C (Data)
C (Clock)
Table 8. Digital audio signals, with the SSM2603 in default slave mode.
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S stream can be seen on Figure 15. Note the one-cycle delay of the data stream
2 3
2
Figure 15. I S timing diagram.
Direction (Zynq POW)
Output
Output
Output
Input
Output
Input/Output
Output
Output
Output
1/f
s
N 1 2 3
Zynq pin
K18
M17
L17
K17
M18
N17
N18
P18
T19
N
2
C. The audio path
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