Digilent ZYBO Reference Manual page 17

ZYBO™ FPGA Board Reference Manual
The HDMI/DVI protocol uses TMDS (Transition-minimized differential signaling) as I/O standard. It is supported on
Zynq by the I/O buffers on the programmable logic side. 50 ohm external parallel termination resistors are
provided on-board. HDMI specifications only require terminations on the Sink side, but optional Source-side
terminations reduce reflections, resulting in improved signal quality. Do not connect powered HDMI/DVI devices to
an unpowered ZYBO, as it might result in back-powering the board through the termination resistors.
Resolutions up to 720p (1280x720) have been tested.
HDMI and DVI are high-speed source-synchronous serial protocols. Implementations on FPGA are required to use
certain built-in primitives to properly synthesize the correct clock frequency, serialize the transmission, and keep a
lock on the signal. The actual implementation of the HDMI/DVI protocols is outside the scope of this manual.
Check for upcoming reference projects on our website or consult relevant specifications and Xilinx documentation.
11 VGA Port
The ZYBO board uses 18 programmable logic pins to create an
analog VGA output port. This translates to 16-bit color depth and
two standard sync signals (HS – Horizontal Sync, and VS – Vertical
Sync).
The digital-to-analog conversion is done using a simple R-2R
2
resistor ladder . The ladder works in conjunction with the 75-ohm
termination resistance of the VGA display to create 32 and 64
analog signal levels red, blue, and green VGA signals. This circuit,
shown in Fig. 8, produces video color signals that proceed in equal
increments between 0V (fully off) and 0.7V (fully on). With 5 bits
each for red and blue and 6 bits for green, 65,536 (32×32×64)
different colors can be displayed, one for each unique 16-bit
pattern.
A video controller circuit must be created in programmable logic
to drive the sync and color signals with the correct timing in order
to produce a working display system.
2
http://en.wikipedia.org/wiki/Resistor_ladder
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Pin 1: Red
5 1
Pin 2: Grn
10 6 Pin 3: Blue
Pin 13: HS
15
11
Pin 14: VS
536W
RED5
F19
270W
536W
RED4
G20
270W
536W
RED3
J20
270W
536W
RED2
L20
270W
536W
RED1
M19
536W
536W
GRN5
F20
270W
536W
GRN4
H20
270W
536W
GRN3
J19
270W
536W
GRN2
L19
270W
536W
GRN1
N20
270W
536W
GRN0
H18
536W
536W
BLU5
G19
270W
536W
BLU4
J18
270W
536W
BLU3
K19
270W
536W
BLU2
M20
270W
536W
BLU1
P20
536W
100W
HSYNC
P19
100W
VSYNC
R19
Zynq- 7
Figure 8. ZYBO VGA circuit.
Pin 5: GND
Pin 6: Red GND
Pin 7: Grn GND
Pin 8: Blu GND
Pin 10: Sync GND
RED
GRN
BLU
HS
VS
HD-DB15F
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