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Functions
2.3 Overcurrent protection (optional)
Figure 2-12
Logic diagram of the I>> stage
1
)
The output indications associated with the trip signals can be found in Table 2-3
2
)
The output indications associated with the trip signals can be found in Table 2-4
Definite time overcurrent stage I>
The logic of the overcurrent stage I is the same as that of the I>> stages. In all references Iph>> must merely
be replaced with Iph> or 3I0>> PICKUP with 3I0>. In all other respects Figure 2-12 applies.
Inverse time overcurrent stage I
The logic of the inverse overcurrent stage also operates chiefly in the same way as the remaining stages. How-
ever, the time delay is calculated here based on the type of the set characteristic, the intensity of the current
and a time multiplier (following figure). A pre-selection of the available characteristics was already carried out
during the configuration of the protection functions. Furthermore, an additional constant time delay T Ip Add
or T 3I0p Add may be selected, which is added to the inverse time. The possible characteristics are shown
in the Technical Data.
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SIPROTEC, 7VK61, Manual
C53000-G1176-C159-3, Release date 05.2009
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