Supermicro C9Z390-PGW User Manual page 87

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CPU Configuration
The following CPU information will be displayed:
Type - the brand, model name, model number of the CPU, and its
rated clock speed
ID - the unique CPU ID
Speed - the detected CPU speed
L1 Data Cache - displays if Level 1 cache is supported
L1 Instruction Cache - displays if Level 1 instruction cache is
supported
L2 Cache - displays if Level 2 cache is supported
L3 Cache - displays if Level 3 cache is supported
VMX - displays if VMX is supported
SMX/TXT - displays if SMX/TXT is supported
C6DRAM
This feature enables moving DRAM contents to PRM memory when the
CPU is in a C6 state. The options are Disabled or Enabled.
SW Guard Extension (SGX)
Select Enabled to activate the Software Guard Extensions (SGX). The
options are Enabled, Disabled, and Software Controlled.
Select Owner EPOCH Input Type
There are three Owner EPOCH modes (each EPOCH is 64 bit). The
options are No Change in Owner EPOCHs, Change to New Random
Owner EPOCH, and Manual User Defined Owner EPOCHs.
Hardware Prefetcher
(Available when supported by the CPU)
If set to Enabled, the hardware prefetcher will prefetch streams of data
and instructions from the main memory to the L2 cache to improve
CPU performance. The options are Disabled or Enabled.
4-21
Chapter 4: AMI BIOS

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