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To configure the analyzer clock
The emulation-bus analyzer can capture bus cycles at data rates up to 25 MHz.
The trace state and time counters are limited to lower speeds. The MC68020
processor is set to a slow analyzer clock by default, and does not need to be
modified because the data rate is sufficiently low, even at the maximum clock
rate of 33 MHz.
By default, the MC68030/EC030 analyzer data rate is set to veryfast. This
processor has more complicated requirements due to the burst and
synchronous access modes. The analyzer can capture all types of bus cycles
correctly up to the maximum clock rate of 40 MHz, but it cannot count states
or time at those higher speeds for certain bus cycle types.
• Answer the question:
Set the analyzer speed:
slow
for a data rate less than or equal to 16.67 MHz.
fast
for a data rate between 16.67 and 20 MHz.
veryfast
for a data rate between 20 and 25 MHz.
The worst-case situation occurs during a zero-wait state burst cycle. The data
rate for burst cycles is given by the equation:
Processor Clock Rate
Data Rate =
(1 + number of wait states)
To determine the correct answer to this question in the MC68030/EC030
emulator, calculate the maximum data rate by using the above equation.
Remember that the emulator always inserts one wait state for all synchronous
and burst accesses to emulation memory, and also must insert one wait state
for synchronous and burst accesses to target memory when the external clock
is greater than or equal to 25 MHz. Then choose the data rate option
according to the data rate you calculate.
Chapter 10: Configuring the Emulator
Emulator Configuration Items
323
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