HP B1476 68020 User Manual page 213

Bus
8 Bits
Cycle
addr (data)
1 1002 (0102 0102)
2 1003 (0202 3f02)
3 1004 (3fff 3fff)
4 1005 (ffff ffff)
The number of cycles and the data bus values will vary depending on memory
bus width, data size, and data address alignment. You must consider these
factors when specifying triggers containing both address and data values.
The second form of problem occurs when a C variable is written, but the
address never appears on the bus. To demonstrate this problem, consider a
32-bit C variable foo at address 0x1002 and a "wild pointer" pointing to
address 0x1000 . A 32-bit write indirect through the pointer will overwrite
part of variable foo , but if the memory bus width is 32 bits, the address of foo
( 0x1002 ) will never appear on the address bus. Similarly, a write indirect
through a wild pointer pointing to address 0x1004 will overwrite part of foo
without the address of foo appearing on the bus. This limitation can be
overcome by specifying an address range when triggering on a symbol that you
suspect is being modified by a wild pointer.
Limitations when Triggering on Instruction Fetches. Instructions located
on odd word address boundaries can be traced by specifying address values
with the mask operator. For example, if foo is located on an odd word
address boundary, the command:
Trace Trigger Address Is foo &= 0xfffffffc
will let the trace function trigger on variable foo . The mask operator can also
be specified as shown in the following command:
Trace Trigger Address Is foo &=~3
The tilde operator (~ ) performs the one's complement operation in a C
expression.
The debugger will apply the appropriate mask for all instruction fetches if you
use the Debugger Option Trace Fetch_Align command.
Chapter 6: Making Trace Measurements
Memory Bus Width
16 Bits
addr (data)
1002 (0102 0102))
1004 (3fff 3fff)
32 Bits
addr (data)
1002 (0102 0102))
1004 (3fff 3fff)
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