Aaeon Gene-5310 Manual page 66

CPU to PCI Write Buffer
When this field is enabled, writes from the CPU to the PCI bus
are buffered, to compensate for the speed differences between the
CPU and PCI bus. When, disabled, the writes are not buffered
and the CPU must wait until the write is complete before starting
another write cycle.
PCI Dynamic Bursting
When enabled, every write transaction goes to the write buffer.
Burstable transactions then burst on the PCI bus and
nonburstable transactions do not.
PCI Master 0 WS Write
When enabled, writes to the PCI bus are executed with zero wait
states.
PCI Delay Transaction
The chipset has an embedded 32 -bit posted write buffer to
support delay transactions cycles. Select enabled to support
compliance with PCI specification version 2.1.
PCI#2 Access #1 Retry
When disabled, PCI#2 will be connected until access finishes
(default). When enabled, PCI#2 will be disconnected if max
retries are attempted without success.
Chapter 3 Award BIOS Setup 57