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SDRAM Cycle Length
This field sets the CAS latency timing.
The choices: 3, 2
DRAM Read Pipeline
The choices: Enable, disable.
Sustained 3T Write
You may enable this field when pipelined burst synchronous
SRAM 9PBSRAM cache memory is installed. It enables sustain
three cycle write access for PBSRAM access at 66 or 75 MHz
Cache P/CPU W Pipeline
The choices: Enable, disable.
Cache Timing
For a secondary cache of one bank, select faster. For a secondary
cache of two banks, select fastest.
The choices: Fast, Fastest
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GENE-5310 User Manual
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