Progress Code
0xB0
Detect DIMM population
0xB1
Set DDR4 frequency
0xB2
Gather remaining SPD data
0xB3
Program registers on the memory controller level —n/a—
0xB4
Evaluate RAS modes and save rank information
0xB5
Program registers on the channel level
0xB6
Perform
sequence
0xB7
Train DDR4 ranks
0x01
0x02
0x03
0x04
0x05
0xB8
Initialize CLTT/OLTT
0xB9
Hardware memory test and init
0xBA
Execute software memory init
0xBB
Program memory map and interleaving
0xBC
Program RAS configuration
0xBF
MRC is done
Table 11. MRC Progress Codes
Main Sequence
the
JEDEC
defined
Subsequences/Subfunctions
—n/a—
—n/a—
—n/a—
—n/a—
—n/a—
initialization
—n/a—
—n/a—
Read DQ/DQS training
Receive Enable training
Write Leveling training
Write DQ/DQS training
DDR channel training done
—n/a—
—n/a—
—n/a—
—n/a—
—n/a—
—n/a—