Spi; Ecspi1 - Dave Embedded Systems AXEL LITE Hardware Manual

AXEL LITE Hardware Manual
7.7

SPI

AXEL LITE provides up to five SPI ports connected to the I.MX6
integrated Enhanced Configurable SPI (ECSPI) controller, featuring:
● Full-duplex synchronous serial interface
● Master/Slave configurable
● Up to four Chip Select (SS) signals to support multiple peripherals
● Transfer continuation function allows unlimited length data transfers
● 32-bit wide by 64-entry FIFO for both transmit and receive data
● Configurable Polarity and phase of the Chip Select (SS) and SPI Clock
(SCLK)
● Direct Memory Access (DMA) support
7.7.1

ECSPI1

AXEL LITE on-board bootable SPI Flash is interfaced with the i.MX6
SoC through the eCSPI1 port on chip select 0. For further details, please
refer to Section 3.3.
The following table describes the interface signals:
ECSPI1_MISO
ECSPI1_MOSI
ECSPI1_RDY
ECSPI1_SCLK
ECSPI1_SS0
ECSPI1_SS1
Pin name Conn.
Pin
J2.93
J2.70
J2.182
J2.91
J2.68
J2.180
J2.54
J2.89
J2.66
J2.178
J2.95
J2.72
J2.184
J2.97
Function
Master data in; slave
data out
Master data out; slave
data in
Data ready signal
Clock signal
Chip select 0 signal
Chip select 1 signal
October, 2016
v. 0.9.5
Notes
48/63