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AXEL LITE Hardware Manual
5.2
Reset scheme and control signals
The following picture shows the simplified block diagram of reset scheme
and voltage monitoring.
RESETBMCU
PMIC
PF0100 E0
PWRO
N
STANDB
Y
SDWN
B
INTB
The available reset signals are described in detail in the following
sections.
5.2.1
CPU_PORn
The following devices can assert this active-low signal:
● PMIC
● multiple-voltage monitor: this device monitors several critical power
voltages and triggers a reset pulse in case any of these exhibits a brownout
PMIC_VSNVS
150
K
PMIC_VSNVS
10K
PMIC_VSNVS
68K
3.3VIN
68K
POR
BOOT_MODE1
BOOT_MODE0
i.MX6
CPU
1K
PMIC_ON_REQ
PMIC_STB_REQ
SPI
NOR
FLASH
VOLTAGE
MONITOR
October, 2016
v. 0.9.5
PMIC_VSNVS
10K
BOOT_MODE1
BOOT_MODE0
10K
CPU
Module
Connectors
PMIC_PWRON
CPU_PORn
PMIC_SDWNB
PMIC_INT_
B
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