Parallel Rgb - Dave Embedded Systems AXEL LITE Hardware Manual

AXEL LITE Hardware Manual
HDMI_CLK_P
HDMI_D0_N
HDMI_D0_P
HDMI_D1_N
HDMI_D1_P
HDMI_D2_N
HDMI_D2_P
HDMI_CEC
HDMI_DDC_SCL
HDMI_DDC_SDA
HDMI_HPD
7.4.3

Parallel RGB

The Parallel Display interface provided by AXEL LITE is derived directly
from the DI0 port of the IPU, bypassing all the i.MX6 integrated display
bridges.
The following table describes the interface signals:
DI0_DISP_CLK
DI0_PIN2
DI0_PIN3
DI0_PIN15
DISP0_DAT0
DISP0_DAT1
DISP0_DAT2
DISP0_DAT3
DISP0_DAT4
Pin name Conn.
Pin
J2.113
J2.115
J2.117
J2.119
J2.121
J2.123
J2.125
J2.127
J2.101
J2.103
J2.129
Pin name Conn.
Pin
J2.132
J2.130
J2.128
J2.124
J2.134
J2.136
J2.138
J2.140
J2.142
Function
signal
HDMI positive clock
signal
HDMI negative data 0
HDMI positive data 0
HDMI negative data 1
HDMI positive data 1
HDMI negative data 2
HDMI positive data 2
HDMI CEC signal
HDMI I2C clock signal
HDMI I2C data signal
HDMI HPD signal
Function
Pixel clock
Horizontal
synchronization
Vertical synchronization
Data valid/blank, data
enable
Pixel data bit 0
Pixel data bit 1
Pixel data bit 2
Pixel data bit 3
Pixel data bit 4
October, 2016
v. 0.9.5
Notes
Notes
44/63