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Figure
1-2, a detailed block diagram of the processor, shows its architec-
tural features.
DSP Core
DAG1
DAG2
8x4x32
8x4x24
PM Address Bus
24
DM Address Bus
32
PM Data Bus
48
Bus
Connect
DM Data Bus
40
(PX)
Data
Register
File
Barrel
Multiplier
16x40b
Shifter
Figure 1-2. ADSP-21065L block diagram
Figure 1-2
also shows the ADSP-21065L's on-chip buses: the PM (Pro-
gram Memory) bus, made up of the PMA (Program Memory Address) and
PMD (Program Memory Data) buses; the DM (Data Memory) bus, made
up of the DMA (Data Memory Address) and DMD (Data Memory Data)
buses; and the I/O bus, made up of the IOA (I/O Address) and IOD (I/O
Data) buses.
The PM bus can access either instructions or data. During a single cycle,
the processor can access two data operands, one over the PM bus and one
over the DM bus, access an instruction from the cache, and perform a
DMA transfer.
The ADSP-21065L's external port provides the processor's interface to
external memory, which is glueless to an SDRAM; memory-mapped I/O;
T
Instruction
D
UAL
cache
32x48b
PROCESSOR
PORT
Program
ADDR
Sequencer
ADDR
ALU
ADSP-21065L SHARC User's Manual
Dual-Ported SRAM
I
WO
NDEPENDENT
-P
B
ORTED
LOCKS
I/O
PORT
DATA
DATA
ADDR
DATA
DATA
ADDR
IOD
IOA
48
17
DMA
IOP
Controller
Registers
SPORT 0
Control,
Status, Timer,
SPORT 1
&
Data Buffers
I/O Processor
,QWURGXFWLRQ
JTAG
7
Test &
Emulation
External Port
SDRAM Interface
Multiprocessor
Interface
HOST Port
Addr Bus
24
Mux
Data Bus
32
Mux
4
(2 Rx, 2 Tx)
(I 2 S)
(2 Rx, 2 Tx)
(I 2 S)
1-3
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