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The ADSP-21065L has four external hardware interrupts: three gen-
eral-purpose interrupts IRQ
processor also has internally generated interrupts for the timer, DMA con-
troller operations, circular buffer overflow, stack overflows, arithmetic
exceptions, multiprocessor vector interrupts, and user-defined software
interrupts.
For the general-purpose external interrupts and the internal timer inter-
rupt, the ADSP-21065L automatically stacks the arithmetic status and
mode (MODE1) registers in parallel with the interrupt servicing. This
enables four nesting levels of very fast service for these interrupts.
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Many of the processor's registers have alternate registers that applications
can activate and use during interrupt servicing to implement a fast context
switch.
Each of the data registers in the Register File, the DAG registers, and the
multiplier result register have alternates. Registers active at reset are called
primary registers, and the others are called alternate (or secondary ) regis-
ters. Control bits in a mode control register determine which set of
registers is active at any particular time.
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The ADSP-21065L instruction set provides a wide variety of program-
ming capabilities. Multifunction instructions enable computations in
parallel with data transfers and as simultaneous multiplier and ALU
operations.
The addressing power of the ADSP-21065L provides flexibility in moving
data both internally and externally. Every instruction can be executed in a
single processor cycle. The ADSP-2106x Family Assembly language uses
, and a special interrupt for reset. The
ADSP-21065L SHARC User's Manual
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1-15
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