Analog Devices SHARC ADSP-21065L User Manual page 24

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Figure 1-4 shows how the ADSP-21065L's design optimally balances its
high-performance DSP core with its high-speed I/Os.
CLK
30 MHz
SDRAM
Figure 1-4. Balanced performance between the DSP core and I/O
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The following publications can be ordered from any Analog Devices sales
office.
ADSP-21000 Family Hardware & Software Development Tools
Data Sheet
ADSP-21065L SHARC Data Sheet
C Compiler Guide and Reference for the ADSP-2106x Family DSPs
Debugger Tutorial for the ADSP-2106x Family DSPs
VisualDSP Debugger Guide and Reference
VisualDSP Release Notes
VisualDSP User's Guide and Reference
1-24 ADSP-21065L SHARC User's Manual
Host
Micro
120 Mbytes/s
ADSP-21065L
60 MHz
120 Mbytes/s
ADSP-21065L
60 MHz
Codec
SRAM