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commonly used by audio codecs), and TDM (Time Division Multiplex)
multichannel mode.
The serial ports can operate with little-endian or big-endian transmission
formats, with selectable word lengths of three to thirty-two bits. They
offer selectable synchronization and transmit modes and optional µ-law or
A-law companding. Serial port clocks and frame syncs can be internally or
externally generated. The serial ports also include keyword and keymask
features to enhance interprocessor communication.
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The ADSP-21065L's on-chip DMA controller enables zero-overhead data
transfers without processor intervention. The DMA controller operates
independently and invisibly to the processor's core, enabling DMA opera-
tions to occur while the core is simultaneously executing its program.
Applications can use DMA transfers to download both code and data to
the ADSP-21065L.
DMA transfers can occur between the ADSP-21065L's internal memory
and external memory, the processor's serial ports, external peripherals, or a
host processor. DMA transfers between external memory and external
peripheral devices are another option. During DMA transfers, the DMA
controller automatically packs and unpacks external bus words.
Ten channels of DMA are available on the ADSP-21065L—eight via the
serial ports and two via the processor's external port (for either host pro-
cessor or other ADSP-21065L memory or I/O transfers).
Asynchronous off-chip peripherals can control the two external port DMA
channels using the DMA request and grant lines (DMAR
and
DMAG
).
Other DMA features include interrupt generation upon completion of
DMA transfers and DMA chaining for automatically linked DMA
transfers.
ADSP-21065L SHARC User's Manual
1-19
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