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• Host port and multiprocessor interface.
• DMA controller to support ten DMA channels.
• Serial ports with two receivers and two transmitters that support
TDM and I
• Two programmable timers and twelve programmable, general-pur-
pose I/O ports.
• JTAG test access port.
Figure 1-1
shows the ADSP-21065L's Super Harvard Architecture, which
consists of a crossbar bus switch connecting the DSP core's numeric pro-
cessor to an independent I/O processor, dual-ported memory, and parallel
system bus port.
Numeric
Processor
Figure 1-1. Super Harvard Architecture
1-2
ADSP-21065L SHARC User's Manual
2
S.
Dual-Ported,
Multiaccess
Memory
Parallel System
Crossbar Bus
Bus Port
Interconnect
I/O Processor
&
DMA Controller
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