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The floating-point operations are single-precision, IEEE-compatible. The
32-bit floating-point format is the standard IEEE format, while the 40-bit
IEEE extended-precision format has eight additional LSBs of mantissa for
greater accuracy.
The computation units perform single-cycle operations—there is no com-
putation pipeline. The units connect in parallel rather than serially. On
the next cycle, the output of any unit can be the input of any other unit.
In a multifunction computation, the ALU and multiplier perform inde-
pendent, simultaneous operations.
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Applications use a general-purpose data Register File to transfer data
between the computation units and the data buses and to store intermedi-
ate results.
For fast context switching, the Register File has two sets (primary and
alternate) of sixteen registers. All of the registers are 40-bits wide. The
Register File, combined with the core's Super Harvard architecture,
enables unconstrained data flow between the computation units and inter-
nal memory.
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A program sequencer and two dedicated address generators supply
addresses for memory accesses. Together the Program Sequencer and Data
Address Generators (DAGs) enable computational operations to execute
with maximum efficiency since they free up the computation units to pro-
cess data exclusively.
Using its instruction cache, the ADSP-21065L can simultaneously fetch
an instruction (from the cache) and access two data operands (from
memory).
The data address generators implement circular data buffers in hardware.
ADSP-21065L SHARC User's Manual
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1-11
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