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On the ADSP-21065L, data memory stores data operands, and program
memory stores both instructions and data (filter coefficients, for example).
This configuration enables the processor to perform dual data fetches
when the instruction cache supplies the instruction.
The data memory address comes from one of two sources—an absolute
value specified in the instruction code (direct addressing) or the output of
a data address generator (indirect addressing).
Nearly every register in the ADSP-21065L's core is classified as a universal
register. Instructions are provided specifically for transferring data
between universal registers or between a universal register and memory
and for performing bitwise operations on their contents. Control registers,
status registers, and individual data registers in the Register File are all
universal registers.
The PX (bus connect) registers provide the path to pass data between the
48-bit PM Data bus and the 40-bit DM Data bus or between the 40-bit
Register File and the PM Data bus. The hardware that implements these
registers handles the 8-bit difference in width.
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The ADSP-21065L provides two independent programmable timer
blocks. Each block can function in one of two modes—Timer Counter
mode or Pulse Count and Capture mode.
In Timer Counter mode, the processor can generate a waveform with an
arbitrary pulse width within a maximum period of 71.5 seconds. In Pulse
Count and Capture mode, the processor can measure either the high or
the low pulse width and period of an input waveform.
The ADSP-21065L provides twelve programmable, general-purpose I/O
pins that can function as either input or output. As output, these pins can
signal peripheral devices; as input, they can provide the test for condi-
tional branching.
1-14
ADSP-21065L SHARC User's Manual
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