YASKAWA VIPA System 300S+ Manual page 37

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VIPA System 300S
Order no.
Time
Real-time clock buffered
Clock buffered period (min.)
Type of buffering
Load time for 50% buffering period
Load time for 100% buffering period
Accuracy (max. deviation per day)
Number of operating hours counter
Clock synchronization
Synchronization via MPI
Synchronization via Ethernet (NTP)
Address areas (I/O)
Input I/O address area
Output I/O address area
Process image adjustable
Input process image preset
Output process image preset
Input process image maximal
Output process image maximal
Digital inputs
Digital outputs
Digital inputs central
Digital outputs central
Integrated digital inputs
Integrated digital outputs
Analog inputs
Analog outputs
Analog inputs, central
Analog outputs, central
Integrated analog inputs
Integrated analog outputs
Communication functions
PG/OP channel
Global data communication
Number of GD circuits, max.
Size of GD packets, max.
HB140 | CPU | 317-4PN23 | en | 18-01
317-4PN23
ü
6 w
Vanadium Rechargeable Lithium Battery
20 h
48 h
10 s
8
ü
Master/Slave
Slave
8192 Byte
8192 Byte
ü
256 Byte
256 Byte
8192 Byte
8192 Byte
65536
65536
1024
1024
-
-
4096
4096
256
256
-
-
ü
ü
8
22 Byte
Hardware description
Technical data
37