I/O Signals For Programmable Controller Cpu; List Of I/O Signals - Mitsubishi QD60P8-G User Manual

3 SPECIFICATIONS

3.3 I/O signals for Programmable Controller CPU

3.3.1 List of I/O signals

Input signal (Signal direction:
QD60P8-G programmable controller CPU)
Device No.
X0
X1 Operating condition setting complete flag
X2
to
X7
X8 CH1
X9 CH2
XA CH3
XB CH4
XC CH5
XD CH6
XE CH7
XF CH8
X10 CH1
X11 CH2
X12 CH3
X13 CH4
X14 CH5
X15 CH6
X16 CH7
X17 CH8
X18
to
X1F
3 - 4
The following table indicates the I/O signals of the QD60P8-G for the programmable
controller CPU.
The I/O numbers (X/Y) and I/O addresses indicated in this chapter and later assume
that the QD60P8-G is installed on the I/O slot No. 0 of the main base unit.
Signal name
Module READY
Reserved (N/A) *
Error occurrence
Accumulating counter comparison
flag
Reserved (N/A) *
*: Write is inhibited to the I/O (X/Y) reserved for the system.
Output signal (Signal direction:
programmable controller CPU
Device No.
Y0
Y1 Operating condition setting request flag
Y2
to
Y7
Y8 CH1
Y9 CH2
YA CH3
YB CH4
YC CH5
YD CH6
YE CH7
YF CH8
Y10 CH1
Y11 CH2
Y12 CH3
Y13 CH4
Y14 CH5
Y15 CH6
Y16 CH7
Y17 CH8
Y18 CH1
Y19 CH2
Y1A CH3
Y1B CH4
Y1C CH5
Y1D CH6
Y1E CH7
Y1F CH8
MELSEC-Q
QD60P8-G)
Signal name
Reserved (N/A) *
Reserved (N/A) *
Error reset request
Comparison signal reset request
Count enable
3 - 4