A/D And D/A Control/Status Register; System Test Register - VersaLogic VL-EBX-37 Reference Manual

A/D and D/A Control/Status Register

This register is used to control A/D and D/A conversion.
ADCONSTAT (Read/Write) CAFh (or C9Fh)
D7
Reserved
Bit Mnemonic
D7-D6 Reserved
D5 Reserved
D4 DACLDA0
D3 Reserved
D2 ADCBUSY0
D1 Reserved
D0 ADCONVST0

System Test Register

This register is used for system test and should not be accessed.
SYSTEST (Read/Write) CAEh (or C9Eh)
D7
Reserved
Bit Mnemonic
D7-D0
Reserved
EBX-37 Reference Manual
D6 D5
Reserved Reserved DACLDA0
Table 35: A/D, D/A Control/Status Register Bit Assignments
Description
These bits are reserved. Only write 0 to these bits and ignore all read values.
This bit is reserved. Only write 0 to this bit and ignore read values.
This is a write-only (pulsed) bit. When a '1' is written it will strobe the LDAC signal
on the LTC2634 D/A Converter. Writing a '0' is ignored.
This bit is reserved. Only write 0 to this bit and ignore read values.
This read-only status bit returns the A/D conversion status.
0 – A/D is not busy doing a conversion.
1 – A/D is busy doing a conversion.
This bit is reserved. Only write 0 to this bit and ignore read values.
This is a write-only (pulsed) bit. When a '1' is written it will start a conversion on
the LTC1857 A/D converter. Writing a '0' is ignored.
D6 D5
Reserved Reserved Reserved
Table 36: System Test Register Bit Assignments
Description
These bits are reserved. Only write 0 to these bits and ignore all read values.
D4 D3
Reserved ADCBUSY0
D4 D3
Reserved Reserved
Special Registers
D2 D1 D0
Reserved ADCONVST0
D2 D1 D0
Reserved Reserved
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